MT9092AP Zarlink, MT9092AP Datasheet - Page 24

• Manufacturer Part Number: MT9092AP
• Description: Digital Telephone 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT9092AP

• Package: 44PLCC
• Power Supply Type: Analog
• Typical Supply Current: 8 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

HDLC Control Register 1
Adrec
HRxEN
HTxEN
EOP
FA
Mark Idle
Trans
When high this bit will enable address recognition. This forces the receiver to recognize only those packets having the unique address
When low this bit will disable the HDLC receiver. The receiver will disable after the rest of the packet presently being received is
When low this bit will disable the HDLC transmitter. The transmitter will disable after the completion of the packet presently being
Forms a tag on the next byte written to the Tx FIFO and when set will indicate an EOP byte to the transmitter which will transmit an
Forms a tag on the next byte written to Tx FIFO and when set will indicate to the transmitter that it should abort the packet in which
When low, the transmitter will be in an idle state. When high it is in an Interframe time fill state. These two states will only occur when
When high this bit will enable transparent mode. The HDLC will perform the serial-to-parallel and parallel-to-serial conversion
as programmed in the Receive Address Recognition Registers or if the address is an All-Call address. When low, all packets are
recognized.
finished. When high the receiver will be immediately enabled (depending on the state of CHoEN) and will begin searching for flags,
Go-aheads etc.
transmitted. When high the transmitter will be immediately enabled (depending on the state of CHoEN) and will begin transmitting
data, if any, or go to a Mark idle or Interframe time fill state.
FCS following this byte. This facilitates loading of multiple packets into Tx FIFO. This bit is reset automatically after a write to the Tx
FIFO occurs.
that byte is being transmitted. This bit is reset automatically after a write to the Tx FIFO.
the Tx FIFO is empty.
without inserting or deleting zeros. No CRC bytes are sent or monitored nor are flags, aborts or Go-aheads. No address recognition is
monitored. The receiver or transmitter must be enabled through Control Register 1 as well as setting CH
Adrec HRxEN HTxEN
7
6
5
EOP
4
Zarlink Semiconductor Inc.
FA
3
MT9092
Mark
24
Idle
2
Trans
1
ADDRESS = 03h WRITE/READ VERIFY
0
-
0
EN.
Power Reset Value
0000 0000
Data Sheet