MT9092AP Zarlink, MT9092AP Datasheet - Page 16

• Manufacturer Part Number: MT9092AP
• Description: Digital Telephone 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT9092AP

• Package: 44PLCC
• Power Supply Type: Analog
• Typical Supply Current: 8 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

The Rx FIFO may be reset by setting the Rxfrst bit in the HDLC Control Register 2 (address 05h). The receiver will
be disabled until reception of the next flag. The Status Register will identify the Rx FIFO as being empty although
the actual data in the FIFO will not be reset. Rxfrst will be cleared by the reception of the next received flag pattern.
Data may be received transparently by setting the TRANS bit (address 03h) high. Timing control bit CH
also be set. The receiver will disable protocol functions such as flag/abort/go-ahead/idle detection, zero deletion,
CRC calculation and address comparison. Data is shifted into the Rx FIFO in a byte-wide format. In transparent
mode when an Rx FIFO overflow condition occurs the receiver will continue to write data into the Rx FIFO,
overwriting the last byte. The overflow interrupt condition can only be detected again if the Rx FIFO is reset (Rxfrst
bit at address 05h) since normally the overflow condition is cleared by the reception of the next flag and transparent
data is unlikely to emulate a flag. Also, the Rxfrst bit itself will have to be reset by writing it low since it is usually
reset automatically by the occurrence of the next flag.
Transducer Interfaces
Four standard telephony transducer interfaces are provided by the HPhone-II. These are:
•
RxBS2,
RxBS1
Note
Txstat2,
Txstat1
Rxstat2,
Rxstat1
The handset microphone inputs (transmitter), pins M+/M- and the speakerphone microphone inputs, pins
MIC+/MIC-. The transmit path is muted/not-muted by the MIC EN control bit. Selection of which input pair is
to be routed to the transmit filter amplifier is acomplished by the MIC/HNSTMIC control bit. Both of these
reside in the Transducer Control Register (address 0Eh). The nominal transmit path gain may be adjusted to
either 6.1 dB (suggested for µ-Law) or 15.4 dB (suggested for A-Law). Control of this gain is provided by the
MICA/u control bit (General Control Register, address 0Fh). This gain adjustment is in addition to the
programmable gain provided by the transmit filter and DSP.
-
-
Are status bits from the Rx FIFO.
RxBS2
These two bits are encoded to indicate the present state of Tx FIFO. This is an asynchronous
Txstat2
These two bits are encoded to indicate the present state of Rx FIFO. This is an asynchronous
Rxstat2
event.
event.
If two consecutive first byte signals are received without an intervening last byte, then an
On power-up these bits are in an indeterminate state until the first byte is written to Rx FIFO.
overflow has occurred and the first packet (or packets) are bad. A bad packet indicates that
either a frame abort had occurred or the FCS did not match.
1
0
1
0
0
0
1
1
0
0
1
1
RxBS1
Txstat1
Rxstat1
1
1
0
0
0
1
1
0
0
1
1
0
Byte status
Tx FIFO Status
Rx FIFO Status
last byte (bad packet)
first byte
last byte (good packet)
packet byte
TxFULL
5 OR MORE BYTES (15 if Fltx set)
4 OR LESS BYTES (14 if Fltx set)
TxEMPTY
RxEMPTY
14 OR LESS BYTES (4 if Flrx set)
15 OR MORE BYTES (5 if Flrx set)
RxOVERFLOW EXISTS
Table 2 - HDLC Status Bits
Zarlink Semiconductor Inc.
MT9092
16
Data Sheet
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EN must