MT9092AP Zarlink, MT9092AP Datasheet - Page 13

• Manufacturer Part Number: MT9092AP
• Description: Digital Telephone 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT9092AP

• Package: 44PLCC
• Power Supply Type: Analog
• Typical Supply Current: 8 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

There are three interrupts associated with the transmitter.
TEOP
TxFL
Txunder Transmit underrun:
Disabling, Reset, Transparent Operation and CRC
Disabling the transmitter via the HTxEn bit will occur after the current packet is completely transmitted. The status
and Interrupt registers may still be read and the Tx FIFO and control registers written while the transmitter is
disabled.
The Tx FIFO may be reset by setting the Txfrst bit in the HDLC Control Register 2 (address 05h). The HDLC Status
Register will identify the Tx FIFO as being empty although the actual data in the FIFO will not be reset. Txfrst will be
cleared by the next write to the Tx FIFO.
Transparent data may be sent by setting the TRANS bit (address 03h) high. The transmitter will no longer generate
the flag, abort and idle sequences, nor will it insert zeros and append the FCS. Data will still be transmitted LSB
first. If there is no data in the Tx FIFO or the Tx FIFO empties the last byte transmitted will be repetitively sent until
new data is presented to the FIFO. It will take typically two ST-BUS frames, after writing TRANS, before this mode
begins. Note that CH
Transmission of the FCS field CRC may be inhibited using the Tcrci (Transmit Crc Inhibit) bit at address 05h. While
this bit is set the opening flag followed by the data fields and closing flag is transmitted, including zero insertion, but
the calculated CRC is not. This allows the processor to insert the CRC as part of the data field. This usage is for
V.120 terminal adaptation for synchronous protocol sensitive UI frames.
Receiver
Following initialization and enabling, via the HRxEN bit at address 03h, the receiver begins clocking in serial data
checking for flags (0111 1110), go-aheads (0111 1111 0), and idle channel states (at least fifteen contiguous ones).
Upon detecting a flag the receiver synchronizes itself to the data stream and begins calculating the CRC. If the
packet length, between the flags and after zero deletion, is less than 25 bits the packet is ignored and nothing is
written to the Rx FIFO. If the packet length, after zero deletion, is between 25 and 31 bits a last byte, bad packet
indication is written into the Rx FIFO.
Idle Channel
When the receiver detects at least 15 contiguous ones it declares an idle channel condition exists and sets the
IdleChan bit in the HDLC status register high (address 04h). This bit remains set until the received condition
changes.
Transmit End Of Packet:
Transmit FIFO Low:
Set when the transmitter has finished sending the closing flag of a packet or after an abort
sequence has been completed.
Set when a transition from 5 to 4 bytes in the Tx FIFO has occurred. This is an early warning to
the microprocessor that the FIFO is emptying and should be serviced before it empties
completely; a condition which will result in a transmit underrun unless an EOP or FA byte has
been written to the FIFO. By setting the Fltx bit (address 05h) high the FIFO emptying condition
will occur at the transition from 15 to 14 bytes. This will allow the microport more time to react to
this interrupt condition.
Set when the Tx FIFO empties without the occurrence of an EOP or FA tagged byte. A frame
abort sequence is automatically transmitted under this condition. Note that this register bit
position is shared with the frame abort (FA) interrupt (see receive interrupts). For this bit to reflect
Txunder the Intsel bit in Control Register 2 (address 05h) must be set high.
0
EN must also be set.
Zarlink Semiconductor Inc.
MT9092
13
Data Sheet