MT90870AG Zarlink, MT90870AG Datasheet - Page 84

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MT90870AG

Manufacturer Part Number
MT90870AG
Description
Switch Fabric 12K x 12K/8K x 4K 1.8V/3.3V 272-Pin BGA Tray
Manufacturer
Zarlink
Datasheet

Specifications of MT90870AG

Package
272BGA
Number Of Ports
32
Fabric Size
12K x 12K|8K x 4K
Switch Core
Non-Blocking|Blocking
Port Speed
2.048|4.096|8.192|16.384 Mbps
Operating Supply Voltage
1.8|3.3 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT90870AG2
Manufacturer:
ZARLINK
Quantity:
41
Non-Multiplexed Microprocessor Port Timing
Note:
1. High impedance is measured by pulling to the appropriate rail with R
taken to charge C
Note: There must be a minimum of 30 ns between CPU accesses, to allow the MT90869 device to recognize the
accesses as separate (i.e., a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion
of CS and/or DS (to initiate the next access).
10
12
11
6
7
8
9
A0-A14
D0-D15
READ
D0-D15
WRITE
Address hold after DS rising
Data setup from DTA Low on Read
Data hold on read
Data setup on write
Data hold on write
Acknowledgment Delay:
Acknowledgment Hold Time
Reading/Writing Registers
Reading/Writing Memory
DS
CS
R/W
DTA
L
.
Characteristics
Figure 30 - Motorola Non-Multiplexed Bus Timing
Zarlink Semiconductor Inc.
t
t
ADS
CSS
t
Sym.
t
RWS
t
t
t
t
t
t
WDS
DHW
DDR
DHR
ADH
AKD
AKH
MT90870
t
WDS
84
Min.
14
L
8
8
8
= 1K/1K potential divider, with timing corrected to cancel time
VALID ADDRESS
t
AKD
t
Typ.
DDR
VALID WRITE DATA
VALID READ DATA
Max.
30
85
70
12
Units
t
t
CSH
t
DHW
ns
ns
ns
ns
ns
ns
ns
ns
DHR
t
t
RWH
ADH
t
AKH
C
C
Test Conditions
L
L
=60pF, R
=60pF, R
C
C
C
Data Sheet
Note 1
Note 1
L
L
L
=60pF
=60pF
=60pF
V
V
V
V
V
V
V
TT
TT
TT
TT
TT
TT
TT
L
L
=1K,
=1K

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