MT90870AG Zarlink, MT90870AG Datasheet - Page 28

• Manufacturer Part Number: MT90870AG
• Description: Switch Fabric 12K x 12K/8K x 4K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90870AG

• Package: 272BGA
• Number Of Ports: 32
• Fabric Size: 12K x 12K|8K x 4K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 2.048|4.096|8.192|16.384 Mbps
• Operating Supply Voltage: 1.8|3.3 V

approximately 0ns, -15 ns, -30 ns or -45 ns as shown in Figure 12. For 32 Mb/s streams, the advancement may be
0, -1 cycle, -2 cycles or -3 cycles, which converts to approximately 0ns, -7 ns, -15 ns or -22 ns.
4.0
4.1
The input pin, LORS, selects whether the Local output streams, LSTo0-15 are set to high impedance at the output
of the MT90870 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if required on
a per-channel basis, is invoked through an external interface circuit controlled by the LCSTo0-1 signals. Setting
LORS to a LOW state will configure the output streams, LSTo0-15, to transmit bi-state channel data with per-
channel high-impedance determined by external circuits under the control of the LCSTo0-1 outputs. Setting LORS
to a HIGH state will configure the output streams, LSTo0-15, of the MT90870 to invoke a high-impedance output on
a per-channel basis.
The LORS pin is an asynchronous input and is expected to be hard-wired for a particular system application,
although it may be driven under logic control if preferred.
4.1.1
The data (channel control bit) transmitted by LCSTo0-1 replicates the Local Output Enable Bit (LE) of the Local
Connection Memory, with a LOW state indicating the channel to be set to High Impedance. See Section 12.3,
Local Connection Memory Bit Definition for setting the Local Output Enable Bit (LE).
The LCSTo0-1 outputs transmit serial data (channel control bits) at 16.384 Mb/s, with each bit representing the per-
channel high impedance state for specific streams. Eight output streams are allocated to each control line as
follows:
(See also Pin Description)
•
•
The Channel Control Bit location, within a frame period, for each channel of the Local output streams is presented
in Table 2, LCSTo Allocation of Channel Control Bits to the Output Streams.
Bit Advancement = -2
Bit Advancement = -4
Bit Advancement = -6
LCSTo0 outputs the channel control bits for streams: LSTo0, 2, 4, 6, 8, 10, 12, and 14.
LCSTo1 outputs the channel control bits for streams: LSTo1, 3, 5, 7, 9, 11, 13, and 15.
Bit Advancement = 0
BSTo0-31 /LSTo0-15
BSTo0-31
BSTo0-31 /LSTo0-15
BSTo0-31 /LSTo0-15
Figure 12 - Backplane and Local Output Advancement Timing diagram for Data Rate of 16 Mb/s
Local Port High Impedance Control
Port High Impedance Control
LORS Set LOW
System Clock
131.072 Mhz
/LSTo0-15
(Default)
FP8o
Bit 1
Bit 1
Bit 1
Ch255
Bit 1
Ch255
Bit 0
Ch255
Bit 0
Ch255
Bit 0
Zarlink Semiconductor Inc.
Bit 0
MT90870
Bit 7
28
Bit 7
Bit Advancement, -2
Bit Advancement, -4
Bit Advancement, -6
Bit 7
Bit 7
Bit 6
Bit 6
Ch0
Bit 6
Ch0
Bit 6
Ch0
Bit 5
Ch0
Bit 5
Bit 5
Bit 5
Data Sheet
Bit 4
Bit 4