MT90870AG Zarlink, MT90870AG Datasheet - Page 56

• Manufacturer Part Number: MT90870AG
• Description: Switch Fabric 12K x 12K/8K x 4K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90870AG

• Package: 272BGA
• Number Of Ports: 32
• Fabric Size: 12K x 12K|8K x 4K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 2.048|4.096|8.192|16.384 Mbps
• Operating Supply Voltage: 1.8|3.3 V

Bit
8
7
6
5
4
3
2
1
0
SBERRXB
SBERTXB
PRBSB
LOCKL
PRSTL
CBERL
SBERRXL
SBERTXL
PRBSL
Name
Table 18 - Bit Error Rate Test Control Register (BERCR) Bits (continued)
RESET
0
0
0
0
0
0
0
0
0
Start Bit Error Rate Receiver for Backplane.
A LOW to HIGH transition enables the Backplane BER receiver. The receiver
monitors incoming data for reception of the seed value. When detected, the
LOCK state is indicated (LOCKB) and the receiver compares the incoming
bits with the reference generator for bit equality and increments the
Backplane Bit error Register (BBCR) on each failure. When set LOW, bit
comparison is disabled and the error count is frozen. The error count is stored
in the Backplane Bit Error Register (BBCR).
Start Bit Error Rate Transmitter for Backplane.
A LOW to HIGH transition starts the BER transmission. When set LOW,
transmission is disabled.
BER Mode Select for Backplane.
When set HIGH, a PRBS sequence of length 2
Backplane port. When set LOW, a PRBS sequence of length 2
selected for the Backplane port.
Local Lock (READ ONLY).
This bit is automatically set HIGH when the receiver has locked to the
incoming data sequence. The bit is reset by a LOW to HIGH transition on
SBERRXL
PBER Reset for Local.
A LOW to HIGH transition initializes the Local BER generator to the seed
value.
Clear Bit Error Rate Register for Local.
A LOW to HIGH transition resets the Local internal bit error counter and the
Local bit error (LBERR) register to zero.
Start Bit Error Rate Receiver for Local.
A LOW to HIGH transition enables the Local BER receiver. The receiver
monitors incoming data for reception of the seed value. When detected, the
LOCK state is indicated (LOCKL) and the receiver compares the incoming
bits with the reference generator for bit equality and increments the Local Bit
error Register (LBCR) on each failure. When set LOW, bit comparison is
disabled and the error count is frozen. The error count is stored in the Local
Bit Error Register (LBCR).
Start Bit Error Rate Transmitter for Local.
A LOW to HIGH transition enables the Local BER transmission. When set
LOW, transmission is disabled.
BER Mode Select for Local.
When set HIGH, a PRBS sequence of length 2
port. When set LOW, a PRBS sequence of length 2
Local port.
Zarlink Semiconductor Inc.
MT90870
56
Description
23
23
-1 is selected for the
-1 is selected for the Local
15
-1 is selected for the
15
-1 is
Data Sheet