MT9044AL Zarlink, MT9044AL Datasheet - Page 9

• Manufacturer Part Number: MT9044AL
• Description: Framer E1/OC3/T1 5V 44-Pin MQFP
• Manufacturer: Zarlink

Specifications of MT9044AL

• Package: 44MQFP
• Maximum Data Rate: 2.048 Mbps
• Number Of Transceivers: 1
• Standard Framing Format: E1|OC3|T1
• Maximum Supply Current: 90 mA
• Minimum Single Supply Voltage: 4.5 V
• Maximum Single Supply Voltage: 5.5 V

In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover Mode, the DCO is free running at a frequency equal to the last (less 30 ms to 60 ms) frequency the
DCO was generating while in Normal Mode.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure
5. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1 Divider Circuit,
a DS2 Divider Circuit and an analog PLL to generate the required output signals.
Four tapped delay lines are used to generate a 16.384 MHz, 12.352 MHz, 12.624 MHz and 19.44 MHz signals.
The E1 Divider Circuit uses the 16.384 MHz signal to generate four clock outputs and three frame pulse outputs.
The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.
These outputs have a nominal 50% duty cycle.
The T1 Divider Circuit uses the 12.384 MHz signal to generate two clock outputs. C1.5o and C3o are generated by
dividing the internal C12 clock by four and eight respectively. These outputs have a nominal 50% duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal
50% duty cycle.
The frame pulse outputs (F0o, F8o, F16o, TSP, RSP) are generated directly from the C16 clock.
DPLL
From
ACKi
Figure 5 - Output Interface Circuit Block
Tapped
Tapped
Tapped
Tapped
Delay
Delay
Delay
Delay
Line
Line
Line
Line
Zarlink Semiconductor Inc.
MT9044
12 MHz
16 MHz
19 MHz
12 MHz
9
Analog PLL
DS2 Divider
T1 Divider
E1 Divider
C19o
C1.5o
C3o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
ACKo
C6o
Data Sheet