MT9044AL Zarlink, MT9044AL Datasheet - Page 10

• Manufacturer Part Number: MT9044AL
• Description: Framer E1/OC3/T1 5V 44-Pin MQFP
• Manufacturer: Zarlink

Specifications of MT9044AL

• Package: 44MQFP
• Maximum Data Rate: 2.048 Mbps
• Number Of Transceivers: 1
• Standard Framing Format: E1|OC3|T1
• Maximum Supply Current: 90 mA
• Minimum Single Supply Voltage: 4.5 V
• Maximum Single Supply Voltage: 5.5 V

The T1 and E1 signals are generated from a common DPLL signal. Consequently, the clock outputs C1.5o, C3o,
C2o, C4o, C8o, C16o, F0o, F16o and C6o are locked to one another for all operating states, and are also locked to
the selected input reference in Normal Mode. See Figures 20 and 21.
All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high
capacitance (e.g. 30 pF) loads.
Analog Phase Lock Loop (APLL)
The analog PLL is intended to be used to achieve a 50% duty cycle output clock. Connecting C19o to ACKi will
generate a phase locked 19.44 MHz ACKo output with a nominal 50% duty cycle and a maximum peak_to_peak
unfiltered jitter of 0.174 U.I.. The analog PLL has an intrinsic jitter of less than 0.01 U.I. In order to achieve this low
jitter level a separate pin is provided to power (AVdd) the analog PLL.
Input Impairment Monitor
This circuit monitors the input signal to the DPLL and automatically enables the Holdover Mode (Auto-Holdover)
when the frequency of the incoming signal is outside the auto-holdover capture range (See AC Electrical
Characteristics - Performance). This includes a complete loss of incoming signal, or a large frequency shift in the
incoming signal. When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output
signal locked to the input signal. The holdover output signal is based on the incoming signal 30 ms minimum to
60 ms prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible because the
Holdover Mode is very accurate (e.g., ±0.05 ppm). The the Auto-Holdover circuit does not use TIE correction.
Consequently, the phase delay between the input and output after switching back to Normal Mode is preserved (is
the same as just prior to the switch to Auto-Holdover).
Automatic/Manual Control State Machine
The Automatic/Manual Control State Machine allows the MT9044 to be controlled automatically (i.e., LOS1, LOS2
and GTi signals) or controlled manually (i.e., MS1, MS2, GTi and RSEL signals). With manual control a single mode
of operation (i.e., Normal, Holdover and Freerun) is selected. Under automatic control the state of the LOS1, LOS2
and GTi signals determines the sequence of modes that the MT9044 will follow.
As shown in Figure 1, this state machine controls the Reference Select MUX, the TIE Corrector Circuit, the DPLL
and the Guard Time Circuit. Control is based on the logic levels at the control inputs LOS1, LOS2, RSEL, MS1,
MS2 and GTi of the Guard Time Circuit (See Figure 6).
All state machine changes occur synchronously on the rising edge of F8o. See the Controls and Modes of
Operation section for full details on Automatic Control and Manual Control.
Figure 6 - Automatic/Manual Control State Machine Block Diagram
RSEL
LOS1
LOS2
Select MUX
Reference
To
Automatic/Manual Control
MS1
Zarlink Semiconductor Inc.
State Machine
MS2
Corrector
MT9044
Enable
To TIE
10
To DPLL
Select
State
To and From
Guard Time
Circuit
Data Sheet