MT9044AL Zarlink, MT9044AL Datasheet - Page 4

• Manufacturer Part Number: MT9044AL
• Description: Framer E1/OC3/T1 5V 44-Pin MQFP
• Manufacturer: Zarlink

Specifications of MT9044AL

• Package: 44MQFP
• Maximum Data Rate: 2.048 Mbps
• Number Of Transceivers: 1
• Standard Framing Format: E1|OC3|T1
• Maximum Supply Current: 90 mA
• Minimum Single Supply Voltage: 4.5 V
• Maximum Single Supply Voltage: 5.5 V

Pin Description
PLCC
23,31
Pin #
1,10,
7,28
11
12
13
14
15
16
17
18
2
3
4
5
6
8
9
39,4,17
MQFP
Pin #
1,22
,25
40
41
42
43
44
10
11
12
2
3
5
6
7
8
9
Name
TCLR
TRST
OSCo
C1.5o
AVDD
OSCi
F16o
TCK
SEC
RSP
TSP
F0o
F8o
C3o
V
PRI
V
DD
SS
Ground. 0 Volts.
Test Clock (TTL Input): Provides the clock to the JTAG test logic. This pin is
internally pulled up to V
TIE Circuit Reset (TTL Input): A logic low at this input resets the Time Interval
Error (TIE) correction circuit resulting in a re-alignment of input phase with output
phase as shown in Figure 19. The TCLR pin should be held low for a minimum of
300 ns. This pin is internally pulled down to VSS.
Test Reset (TTL Input): Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin is internally pulled down to VSS.
Secondary Reference (TTL Input). This is one of two (PRI & SEC) input
reference sources (falling edge) used for synchronization. One of three possible
frequencies (8 kHz, 1.544 MHz, or 2.048 MHz) may be used. The selection of the
input reference is based upon the MS1, MS2, LOS1, LOS2, RSEL, and GTi control
inputs (Automatic or Manual). This pin is internally pulled up to V
Primary Reference (TTL Input). See pin description for SEC. This pin is
internally pulled up to V
Positive Supply Voltage. +5V
Oscillator Master Clock (CMOS Output). For crystal operation, a 20 MHz
crystal is connected from this pin to OSCi, see Figure 10. For clock oscillator
operation, this pin is left unconnected, see Figure 9.
Oscillator Master Clock (CMOS Input). For crystal operation, a 20 MHz crystal
is connected from this pin to OSCo, see Figure 10. For clock oscillator operation,
this pin is connected to a clock source, see Figure 9.
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8 kHz 61 ns active
low framing pulse, which marks the beginning of an ST-BUS frame. This is
typically used for ST-BUS operation at 8.192 Mb/s. See Figure 20.
Receive Sync Pulse (CMOS Output). This is an 8 kHz 488 ns active high framing
pulse, which marks the end of an ST-BUS frame. This is typically used for
connection to the Siemens MUNICH-32 device. See Figure 21.
Frame Pulse ST-BUS 2.048 Mb/s (CMOS Output). This is an 8 kHz 244 ns
active low framing pulse, which marks the beginning of an ST-BUS frame. This is
typically used for ST-BUS operation at 2.048 Mb/s and 4.096 Mb/s. See Figure 20.
Transmit Sync Pulse (CMOS Output). This is an 8 kHz 488 ns active high
framing pulse, which marks the beginning of an ST-BUS frame. This is typically
used for connection to the Siemens MUNICH-32 device. See Figure 21.
Frame Pulse (CMOS Output). This is an 8 kHz 122 ns active high framing pulse,
which marks the beginning of a frame. See Figure 20.
Clock 1.544 MHz (CMOS Output). This output is used in T1 applications.
Analog Vdd. +5V
Clock 3.088 MHz (CMOS Output). This output is used in T1 applications.
Zarlink Semiconductor Inc.
DC
MT9044
nominal.
DD
DD
4
.
.
DC
Description
nominal.
DD
.
Data Sheet