ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 74

• Manufacturer Part Number: ZL50110GAG
• Description: CESoP Processor 552-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50110GAG

• Package: 552BGA
• Maximum Data Rate: 1000 Mbps
• Transmission Media Type: Fiber Optic
• Power Supply Type: Analog
• Typical Supply Current: 950(Max) mA
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.65 V
• Maximum Operating Supply Voltage: 1.95 V

7.11
7.11.1
The ZL50110/11/12/14 family supports the following modes of operation.
7.11.1.1
This mode is the device's normal operating mode. Boundary scan testing of the peripheral ring is accessible in this
mode via the dedicated JTAG pins. The JTAG interface is compliant with the IEEE Std. 1149.1-2001; Test Access
Port and Boundary Scan Architecture.
Each variant has it's own dedicated.bsdl file which fully describes it's boundary scan architecture.
7.11.1.2
All output and I/O output drivers are tri-stated allowing the device to be isolated when testing or debugging the
development board.
7.11.2
The System Test Mode is selected using the dedicated device input bus TEST_MODE[2:0] as follows in Table 28.
7.11.3
Selected by TEST_MODE[2:0] = 3'b000. As the test_mode[2:0] inputs have internal pull-downs this is the default
mode of operation if no external pull-up/downs are connected. The GPIO[15:0] bus is captured on the rising edge of
the external reset to provide internal bootstrap options. After the internal reset has been de-asserted the GPIO pins
may be configured by the ADM module as either inputs or outputs.
7.11.4
Selected by TEST_MODE[2:0] = 3'b011. All device output and I/O output drivers are tri-stated.
Test Modes Operation
Overview
Test Mode Control
System Normal Mode
System Tri-state Mode
System Normal Mode
System Tri-State Mode
SYS_NORMAL_MODE
SYS_TRI_STATE_MODE
System Test Mode
Table 28 - Test Mode Control
ZL50110/11/12/14
Zarlink Semiconductor Inc.
74
test_mode[2:0]
3’b000
3’b011
Data Sheet