ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 40

• Manufacturer Part Number: ZL50110GAG
• Description: CESoP Processor 552-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50110GAG

• Package: 552BGA
• Maximum Data Rate: 1000 Mbps
• Transmission Media Type: Fiber Optic
• Power Supply Type: Analog
• Typical Supply Current: 950(Max) mA
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.65 V
• Maximum Operating Supply Voltage: 1.95 V

M1_TXER /
M1_TXD[9]
M1_GTX_CLK
M2_LINKUP_LED
M2_ACTIVE_LED
M2_RXCLK
M2_COL
M2_RXD[3:0]
M2_RXDV
Signal
Signal
Note: This port must not be used to receive data at the same time as port 3,
Table 11 - MII Port 1 Interface Package Ball Definition (continued)
I/O
I/O
I U
I D
I U
I D
O
O
O
O
Table 12 - MII Port 2 Interface Package Ball Definition
N23
N21
G23
AB24
AA19
AE26
[3]
[2]
AA20
MII Port 2 - ZL50111 and ZL50112 variants only.
AD25
AC23
Package Balls
Package Balls
they are mutually exclusive.
ZL50110/11/12/14
Zarlink Semiconductor Inc.
[1]
[0]
MII Port 1
40
AB21
AD24
GMII/MII - M1_TXER
Transmit Error. Transmitted synchronously
with respect to M1_TXCLK, and active high.
When asserted (with M1_TXEN also
asserted) the ZL50110/11/12/14 will transmit
a non-valid symbol, somewhere in the
transmitted frame.
TBI - M1_TXD[9]
Transmit Data. Clocked on rising edge of
M1_GTXCLK.
GMII/TBI only - Gigabit Transmit Clock
Output of a clock for Gigabit operation at
125 MHz.
LED drive for MAC 2 to indicate port is
linked up.
Logic 0 output = LED on
Logic 1 output = LED off
LED drive for MAC 2 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
MII only - Receive Clock.
Accepts the following frequencies:
Collision Detection. This signal is
independent of M2_TXCLK and
M2_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
Receive Data. Clocked on rising edge of
M2_RXCLK.
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M2_RXCLK.
It is asserted when valid data is on the
M2_RXD bus.
25.0 MHz
MII
Description
Description
100 Mbps
Data Sheet