ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 16

• Manufacturer Part Number: ZL50110GAG
• Description: CESoP Processor 552-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50110GAG

• Package: 552BGA
• Maximum Data Rate: 1000 Mbps
• Transmission Media Type: Fiber Optic
• Power Supply Type: Analog
• Typical Supply Current: 950(Max) mA
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.65 V
• Maximum Operating Supply Voltage: 1.95 V

ZL50112 Package view from TOP side. Note that ball A1 is non-chamfered corner.
AA
AC
AD
AF
AB
AE
W
M
G
L
C
D
H
J
N
R
U
A
B
E
K
P
V
Y
F
T
TDM_FRM
TDM_CLKi
RAM_ADD
RAM_ADD
RAM_ADD
RAM_ADD
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_PAR
RAM_PAR
RAM_DAT
RAM_DAT
PLL_SEC RAM_BW
RAM_BW
RAM_BW
GPIO[12] GPIO[13] RAM_DAT
PLL_PRI RAM_BW
GPIO[1]
GPIO[5]
o_REF
A[10]
A[15]
A[21]
A[25]
A[29]
ITY[1]
ITY[7]
R[12]
R[17]
A[34]
A[35]
GND
GND
GND
A[3]
R[5]
R[9]
_H
_E
P
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
TDM_STo[
TDM_STo[
TDM_FRM
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_PAR
RAM_PAR
RAM_ADD
RAM_ADD
RAM_ADD
RAM_ADD
RAM_ADD
RAM_DAT
RAM_DAT
RAM_DAT
RAM_BW
GPIO[11] GPIO[14] RAM_DAT
GPIO[4]
GPIO[7]
i_REF
ITY[0]
ITY[6]
A[13]
A[18]
A[24]
A[28]
R[10]
R[14]
R[18]
A[36]
A[40]
A[50]
A[1]
A[9]
R[4]
R[6]
_G
_A
_D
1]
0]
TDM_CLK
TDM_CLKi
TDM_CLKi
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_PAR
RAM_ADD
RAM_ADD
RAM_ADD
RAM_ADD
RAM_DAT
RAM_DAT
RAM_DAT
TDM_STi[
RAM_BW
RAM_BW
RAM_BW
GPIO[0]
GPIO[6] GPIO[10] RAM_DAT
GPIO[8] GPIO[15] RAM_DAT
_REF
ITY[5]
A[12]
A[16]
A[23]
A[27]
A[31]
R[11]
R[15]
A[37]
A[41]
A[48]
A[55]
A[5]
R[2]
R[7]
o[3]
_B
_C
_F
2]
S
TDM_CLKi
RAM_PAR
RAM_ADD
RAM_ADD
RAM_ADD
RAM_ADD
TDM_STo[
TDM_CLK
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_RW SYSTEM_
SYSTEM_
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
IC_GND
GPIO[3]
ITY[4]
A[14]
A[19]
A[26]
A[30]
R[13]
R[19]
A[38]
A[42]
A[47]
A[54]
A[56]
R[3]
R[8]
RST
o[1]
A[0]
A[4]
A[6]
4]
[3]
RAM_ADD
RAM_ADD
TDM_STo[
TDM_STi[
TDM_STi[
TDM_STi[
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_PAR
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
IC_GND
DEBUG
GPIO[2] VDD_COR
GPIO[9] RAM_DAT
ITY[3]
A[17]
A[22]
R[16]
A[32]
A[39]
A[43]
A[46]
A[53]
A[57]
A[61]
A[11]
GND
GND
GND
A[2]
A[7]
R[0]
5]
4]
3]
0]
TDM_CLKi
VDD_COR
VDD_COR
RAM_ADD
VDD_COR
VDD_COR
TDM_CLK
TDM_CLK
TDM_CLK
RAM_DAT
RAM_DAT
RAM_PAR
SYSTEM_
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
TEST_MO
TDM_STi[
o_REF
A1VDD
ITY[2]
DE[2]
GND
A[20]
GND
A[33]
GND
A[44]
A[49]
A[58]
A[62]
o[6]
o[2]
A[8]
R[1]
CLK
[1]
IC
6]
E
E
E
E
E
TDM_STo[
TDM_STo[
TDM_CLKi
TDM_STo[
TDM_CLKi
VDD_COR
RAM_DAT
RAM_DAT
RAM_DAT
RAM_DAT
JTAG_TDI IC_GND CPU_ADD
JTAG_TR
Figure 3 - ZL50112 Package View and Ball Positions
A[45]
A[51]
A[59]
A[63]
[6]
[0]
ST
7]
6]
3]
E
TDM_CLKi
TDM_STo[
RAM_DAT
RAM_DAT
TEST_MO
TDM_STi[
TDM_CLK
TDM_STi[
TDM_CLK
JTAG_TC
IC_GND CPU_ADD
A[52]
A[60]
DE[0]
o[8]
o[4]
[7]
7]
5]
2]
K
TDM_CLKi
TDM_CLKi
VDD_COR
TDM_CLK
TDM_CLK
TDM_STi[
TDM_CLK
TEST_MO
JTAG_TD
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
IC-GND CPU_ADD
DE[1]
o[10]
o[9]
o[0]
R[3]
R[5]
[9]
[5]
1]
O
E
TDM_CLKi
TDM_CLKi
TDM_CLKi
TDM_STo[
TDM_STo[
TDM_CLK
JTAG_TM
CPU_ADD
CPU_ADD
CPU_ADD
VDD_IO
VDD_IO
R[10]
GND
[10]
o[7]
R[4]
R[7]
R[8]
10]
[4]
[2]
9]
S
ZL50110/11/12/14
TDM_CLKi
TDM_STo[
TDM_CLK
CPU_ADD
CPU_ADD
CPU_ADD
CPU_ADD
CPU_ADD
CPU_ADD
TDM_STi[
TDM_STi[
TDM_STi[
VDD_IO
VDD_IO
Zarlink Semiconductor Inc.
R[13]
R[15]
GND
GND
GND
GND
GND
GND
R[11]
o[5]
R[2]
R[6]
R[9]
[11]
10]
9]
8]
8]
TDM_CLK
TDM_CLKi
TDM_CLK
TDM_CLKi
VDD_COR
CPU_ADD
CPU_ADD
CPU_ADD
CPU_ADD
CPU_ADD
CPU_ADD
TDM_STi[
VDD_IO
VDD_IO
o[13]
o[11]
GND
GND
GND
GND
GND
GND
R[12]
R[14]
R[16]
R[17]
R[18]
R[19]
[12]
11]
[8]
E
TDM_STo[
TDM_CLKi
TDM_STo[
VDD_COR
CPU_ADD
CPU_ADD
CPU_ADD
CPU_ADD
TDM_STi[
TDM_CLK
VDD_IO
VDD_IO
GND
o[12]
GND
GND
GND
GND
GND
GND
R[23]
R[22]
R[21]
R[20]
GND
[13]
12]
12]
11]
E
16
TDM_CLKi
VDD_COR
TDM_STo[
TDM_STi[
TDM_CLK
TDM_STi[
TDM_STo[
CPU_CLK CPU_DRE
CPU_WE CPU_SDA
CPU_OE CPU_TS_
CPU_CS CPU_SDA
VDD_IO
VDD_IO
CPU_TA CPU_DAT
o[14]
GND
GND
GND
GND
GND
GND
[14]
13]
13]
14]
15]
E
TDM_CLKi
VDD_COR
TDM_STo[
CPU_DAT
AUX2_CL
AUX2_CL
AUX2_CL
VDD_IO
VDD_IO
Ko[0]
Ki[0]
Ki[1]
GND
GND
GND
GND
GND
GND
[15]
A[8]
A[1]
CK2
ALE
CK1
14]
Q0
E
TDM_CLK
CPU_DAT
CPU_DAT
CPU_DRE
TDM_STi[
AUX1_CL
AUX1_CL
CPU_IRE
IC_VDD_I
VDD_IO
VDD_IO
o[15]
Ko[1]
GND
GND
GND
GND
GND
GND
A[15]
N/C
Ki[1]
N/C
A[7]
15]
Q1
Q1
IC
O
AUX2_CL
CPU_DAT
CPU_DAT
CPU_DAT
CPU_DAT
CPU_IRE
VDD_IO
VDD_IO
Ko[1]
A[23]
A[12]
A[10]
A[3]
N/C
N/C
N/C
N/C
N/C
Q0
IC
VDD_COR
AUX1_CL
AUX1_CL
CPU_DAT
CPU_DAT
CPU_DAT
CPU_DAT
CPU_DAT
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
Ko[0]
A[22]
A[16]
Ki[0]
N/C
N/C
N/C
N/C
A[6]
A[4]
A[0]
E
M2_RXCL
CPU_DAT
CPU_DAT
CPU_DAT
CPU_DAT
CPU_DAT
A[30]
A[21]
A[14]
N/C
N/C
N/C
N/C
N/C
N/C
A[9]
A[5]
K
VDD_COR
M2_RXDV
M2_TXER M2_RXD[1
CPU_DAT
CPU_DAT
CPU_DAT
CPU_DAT
A[27]
A[20]
A[13]
N/C
N/C
N/C
N/C
N/C
A[2]
E
VDD_COR
VDD_COR
M1_RXER M1_TXCL
VDD_COR
M1_TXD[2
M1_TXD[0
VDD_COR
M0_TXD[7
M0_TXD[2
VDD_COR
M2_TXD[1
M1_GTX_
M0_GTX_
CPU_DAT
CPU_DAT
CPU_DAT
GND
GND
A[24]
A[18]
A[11]
N/C
N/C
N/C
N/C
N/C
N/C
CLK
CLK
IC
E
E
E
E
E
]
]
]
]
]
]
M1_REFC
M1_TXD[6
M1_TXD[3
M1_TXD[1
M0_RXD[2
M0_TXD[5
M0_TXD[1
M0_TXD[0
M0_GIGA
M0_TXER M0_TXEN M0_RXD[4
M0_RXCL
M2_TXEN M2_RXD[2
CPU_DAT
CPU_DAT
CPU_DAT
BIT_LED
GND
GND
GND
A[29]
A[25]
A[17]
N/C
N/C
N/C
N/C
N/C
N/C
LK
IC
K
K
]
]
]
]
]
]
]
M2_LINKU
M1_TXD[5
M1_TXD[4
M0_RXD[5
M0_TXD[6
M0_TXD[4
M0_TXD[3
M0_LINKU
M2_TXD[2
M1_RXCL
M1_TXER M1_RXD[2
M1_TXEN
CPU_DAT
CPU_DAT
M1_CRS
M_MDC
P_LED
P_LED
A[28]
A[19]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
K
]
]
]
]
]
]
]
]
M1_RXD[5
M0_RXD[6
M2_ACTIV
M2_RXD[0
M1_TXD[7
M0_TXCL
M0_RBC0 M0_COL M0_RXD[1
M0_REFC
M2_RXER M2_CRS M0_ACTIV
M2_TXD[0
CPU_DAT
E_LED
A[26]
GND
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
LK
K
]
]
]
]
]
]
]
M1_RXD[7
M1_RXD[3
M1_RXD[4
M1_RBC1 M1_RXD[0
M0_RXDV M0_RXER
M0_RXD[7
M0_RBC1 M0_RXD[0
M1_ACTIV
M2_RXD[3
M2_TXD[3
CPU_DAT
M1_GIGA
BIT_LED
M1_COL M1_RXD[1
M0_CRS M1_RBC0
Data Sheet
E_LED
A[31]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
IC
]
]
]
]
]
]
M1_LINKU
M1_RXDV
M1_RXD[6
M0_RXD[3
M2_TXCL
M_MDIO
M2_COL
P_LED
E_LED
GND
GND
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
IC
K
]
]
]
]
]
]
AA
AC
AD
AF
AB
AE
W
M
G
L
C
D
H
J
N
R
U
A
B
E
K
P
V
Y
F
T