70V9099L12PF IDT, Integrated Device Technology Inc, 70V9099L12PF Datasheet

70V9099L12PF

Manufacturer Part Number
70V9099L12PF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of 70V9099L12PF

Density
1Mb
Access Time (max)
25ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
50MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
34b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
200mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
8b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant
Features:
Functional Block Diagram
NOTE:
1. I/O
©2010 Integrated Device Technology, Inc.
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 9/12ns (max.)
– Industrial: 9ns (max.)
Low-power operation
– IDT70V9199/099L
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
Dual chip enables allow for depth expansion without
additional logic
I/O
0
X
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
0L
CNTRST
- I/O
FT/PIPE
CNTEN
- I/O
7
R/W
ADS
CLK
X
CE
CE
OE
A
8L (1)
for IDT70V9099.
A
16L
0L
1L
0L
L
L
L
L
L
L
L
0/1
1
0/1
0
1
Counter/
Address
Reg.
0
HIGH-SPEED 3.3V
128K x9/x8
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Control
I/O
MEMORY
ARRAY
1
Counter enable and reset features
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data, and
– Data input, address, and control registers
– Fast 9 ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66 MHz operation in Pipelined output mode
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100-pin Thin Quad Flatpack (TQFP)
Green parts available, see ordering information
address inputs
Control
I/O
Counter/
Address
Reg.
0
0/1
0
1
1
IDT70V9199/099L
0/1
R/W
OE
CE
CE
I/O
A
A
CLK
ADS
CNTEN
CNTRST
FT/PIPE
JULY 2010
4859 drw 01
16R
0R
0R
1R
R
0R
R
R
R
- I/O
R
R
R
8R (1)
DSC-4859/7
.

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70V9099L12PF Summary of contents

Page 1

Features: ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed clock to data access – Commercial: 9/12ns (max.) – Industrial: 9ns (max.) ◆ Low-power operation – IDT70V9199/099L Active: 500mW (typ.) Standby: 1.5mW (typ.) ...

Page 2

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Description: The IDT70V9199/099 is a high-speed128K x9/x8 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on ...

Page 3

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Pin Configuration (1,2,3) 04/04/03 Index 100 ...

Page 4

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Pin Names Left Port Right Port Chip Enables 0L, 1L 0R, 1R R/W R/W Read/Write Enable Output Enable ...

Page 5

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Recommended Operating Temperature and Supply Voltage Ambient (2) Grade Temperature O O Commercial + Industrial - +85 C NOTES: 1. This is ...

Page 6

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter CE and CE I Dynamic Operating DD L Current (Both Outputs Disabled, Ports Active MAX ...

Page 7

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT 435Ω Figure 1. AC Output Test load. , tCD 1 ...

Page 8

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) Symbol t Clock Cycle Time (Flow-Through) CYC1 t Clock Cycle Time (Pipelined) CYC2 t Clock High Time ...

Page 9

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE t CH1 CLK ...

Page 10

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of a Bank Select Pipelined Read t CYC2 t CH2 CLK ADDRESS (B1 0(B1) DATA OUT(B1) t ...

Page 11

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Pipelined Read-to-Write-to-Read ( CYC2 t CH2 CLK (4) An ADDRESS ...

Page 12

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Flow-Through Read-to-Write-to-Read ( CYC1 t t CH1 CL1 CLK (4) ...

Page 13

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Pipelined Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK ADDRESS SAD HAD ADS CNTEN (2) Qx ...

Page 14

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs) t CH2 CLK ADDRESS (3) INTERNAL ADDRESS t t SAD HAD ADS (7) ...

Page 15

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Functional Description The IDT70V9199/099 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal ...

Page 16

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Ordering Information XXXXX Device Power Speed Package Type NOTES: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. 2. Green ...

Page 17

IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Datasheet Document History 09/30/99: Initial Public Release 11/12/99: Replaced IDT logo 01/10/01: Page 3 Changed information in Truth Table II Page 4 Increased storage temperature parameters Clarified T Page 5 ...

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