W39V040FAP Winbond Electronics, W39V040FAP Datasheet - Page 6

• Manufacturer Part Number: W39V040FAP
• Manufacturer: Winbond Electronics

Specifications of W39V040FAP

• Density: 4Mb
• Access Time (max): 150ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 4/11Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Program/erase Volt (typ): 3.3V
• Sync/async: Async/Sync
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

W39V040FA
6. FUNCTIONAL DESCRIPTION
6.1 Interface Mode Selection and Description
This device can operate in two interface modes, one is Programmer interface mode, and the other is
FWH interface mode. The IC pin of the device provides the control between these two interface
modes. These interface modes need to be configured before power up or return from #RESET
When
.
IC pin is set to V
the device will be in the Programmer mode; while the IC pin is set to low state (or
DD,
leaved no connection), it will be in the FWH mode. In Programmer mode, this device just behaves like
traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed. The
row address are mapped to the higher internal address A[18:11]. And the column address are
mapped to the lower internal address A[10:0]. For FWH mode, it complies with the FWH Interface
Specification. Through the FWH[3:0] and FWH4 to communicate with the system chipset .
6.2 Read (Write) Mode
In Programmer interface mode, the read (write) operation of the W39V040FA is controlled by #OE
(#WE). The #OE (#WE) is held low for the host to obtain (write) data from (to) the outputs (inputs).
#OE is the output control and is used to gate data from the output pins. The data bus is in high
impedance state when #OE is high. As for in the FWH interface mode, the read or write is determined
by the "bit 0 & bit 1 of START CYCLE ". Refer to the FWH cycle definition and timing waveforms for
further details.
6.3 Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the
device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all
outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device
will return to read or standby mode, it depends on the control signals.
6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP
There are two alternatives to set the boot block. Either 16K-byte or 64K-byte in the top location of this
device can be locked as boot block, which can be used to store boot codes. It is located in the last
16K/64K bytes of the memory with the address range from 7C000(hex)/70000(hex) to 7FFFF(hex).
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout), other memory
locations can be changed by the regular programming method.
Besides the software method, there is a hardware method to protect the top boot block and other
sectors. Before power on programmer, tie the #TBL pin to low state and then the top boot block will
not be programmed/erased. If #WP pin is tied to low state before power on, the other sectors will not
be programmed/erased.
In order to detect whether the boot block feature is set on or not, users can perform software
command
sequence:
enter
the
product
identification
mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address
7FFF2(hex). If the DQ0/DQ1 output data is "1," the 64Kbytes/16Kbytes boot block programming
lockout feature will be activated; if the DQ0/DQ1 output data is "0," the lockout feature will be
inactivated and the boot block can be erased/programmed. But the hardware protection will override
the software lock setting, i.e., while the #TBL pin is trapped at low state, the top boot block cannot be
programmed/erased whether the output data, DQ0/DQ1 at the address 7FFF2, is "0" or "1". The #TBL
will lock the whole 64Kbytes top boot block, it will not partially lock the 16Kbytes boot block. You can
- 6 -