W83781D Nuvoton Technology Corporation of America, W83781D Datasheet - Page 10

• Manufacturer Part Number: W83781D
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83781D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Continued
# Indicates Active Low("Not")
7. FUNCTIONAL DESCRIPTION
7.1 General Description
The W83781D/G provides 5 analog positive inputs, 2 analog negative input, 3 fan speed monitors or
fan ON/OFF control, 3 thermistor voltage inputs, case open detection and beep function output when
the monitor value exceed the set limit value. When start the monitor function on the chip, the watch
dog machine monitor every function and store the value to registers. If the monitor value exceeds the
limit value, the interrupt status will be set to 1.
The W83781D/G provides two interface for microprocessor to read/write internal registers. The first
interface use ISA Bus to access which the ports of low byte (bit2~bit0) are defined in the port 5h and
6h. The high byte of these ports is decoded by Chip Select (CS#), the general decoded address is set
to port 295h and port 296h. These two ports are described as following:
Port 295h: W83781D/G Index register port.
Port 296h: Data port.
-12VIN
+12VIN
+5VIN
+3.3VIN
VCOREB
VCOREA
VREF
VTIN3
VTIN2
VTIN1
VID0
OVT#
IRQ
SMI#
A2-A0
CS#
PIN NAME
PIN NO.
45-47
31
32
33
34
35
36
37
38
39
40
41
42
43
44
48
OUT
AOUT
TYPE
OD
OD
AIN
AIN
AIN
AIN
AIN
AIN
AIN
AIN
AIN
IN
IN
IN
t
12
12
t
t
12t
Ground-referred inverting op amp input.
0V to 4.096V FSR Analog Inputs.
This pin is Analog Vcc and connects internal monitor
channel IN3 with fixed scale.
0V to 4.096V FSR Analog Inputs.
0V to 4.096V FSR Analog Inputs.
0V to 4.096V FSR Analog Inputs.
Reference Voltage.
Thermistor 3 terminal input.
Thermistor 2 terminal input.
Thermistor 1 terminal input.
Voltage Supply readouts from P6.This value is read in the
VID/Fan Divisor Register.
Over temperature Shutdown Output.
Interrupt Request.
System Management Interrupt (open drain). This output is
enabled when Bit 1 in the Configuration Register (CR40)
is set to 1. The default state is disabled.
The three lowest order bits of the 16-bit ISA Address Bus.
A0 corresponds to the lowest order bit.
Chip Select input from an external decoder which
decodes high order address bits on the ISA Address Bus.
This is an active low input.
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DESCRIPTION
Publication Release Date: April 14, 2005
W83781D/W83781G
Revision 2.0