W83781D Nuvoton Technology Corporation of America, W83781D Datasheet
W83781D
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W83781D Summary of contents
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... W83781D/W83781G WINBOND H/W MONITORING W83781D/W83781G Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Interrupt Status Register 2 – Index 42h (Bank 0) ......................................................... 19 8.6 SMI# Mask Register 1 – Index 43h (Bank 0)............................................................... 20 8.7 SMI# Mask Register 2 – Index 44h (Bank 0)................................................................ 20 8.8 IRQ Mask Register 2 – Index 45h (Bank 0).................................................................. 21 W83781D/W83781G Publication Release Date: April 14, 2005 - II - Revision 2.0 ...
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... Temperature Sensor 2 Over-temperature(High Byte) Register – Index 55h (Bank 1). 35 8.34 Temperature Sensor 2 Over-temperature (Low Byte) Register – Index 56h (Bank 1)......... 35 8.35 Temperature Sensor 3 Temperature Register - Index 50h (Bank 2)............................ 36 W83781D/W83781G Publication Release Date: April 14, 2005 - III - Revision 2.0 ...
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... Absolute Maximum Ratings .......................................................................................... 40 9.2 DC Characteristics........................................................................................................ 40 9.3 AC Characteristics ........................................................................................................ 42 9.3.1 ISA Read/Write Interface Timing ....................................................................................42 9.3.2 Serial Bus Timing Diagram.............................................................................................44 10. HOW TO READ THE TOP MARKING...................................................................................... 45 11. PACKAGE DIMENTIONS ......................................................................................................... 46 12. APPLICATION CIRCUITS OF W83781D ................................................................................. 47 REVISION HISTORY ............................................................................................................................ 49 W83781D/W83781G Publication Release Date: April 14, 2005 - IV - Revision 2.0 ...
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... The W83781D hardware monitoring IC for personal computers, server computers, or microprocessor based systems. W83781D/G can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stablely and properly. W83781D provides both 2 TM ...
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... ISA and I C serial bus interface • 5 VID input pins for CPU Vcore identification • Initial power fault beep (for +3.3V, VcoreA) • Master reset input to W83781D/G • Independent power plane of digital Vcc and analog Vcc (input to IC) TM • Intel LDCM compatible • ...
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... VID4 Input VTIN3 : : : VTIN1 FAN3 FAN : : Speed : FAN1 Counter CASEOPEN (Serial Bus) Configure and Control Registers ISA/Serial Bus Interface (ISA Bus Interface W83781D/W83781G SMI# Watch-Dog IRQ and Interrupt Status Registers OVT# BEEP / GPO# RSTOUT Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Open-drain output pin with 12 mA sink capability Open-drain output pin with 48 mA sink capability TTL level input pin TTL level input pin and schmitt trigger ts AIN - Input pin(Analog W83781D Publication Release Date: April 14, 2005 - 4 - W83781D/W83781G VID2 RSTOUT FAN1 IN/OUT FAN2 IN/OUT FAN3 IN/OUT VID4 CASEOPEN Revision 2.0 ...
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... CASE OPEN. An active high input from an external circuit which latches a Case Open event. This line can go high without any clamping action intrusion regardless of the I/O powered state of the W83781D/G. The W83781D/G 12t provides an internal open drain on this line, controlled by Bit 7 of IRQ Mask Register 2, to provide a minimum 20 ms reset of this line ...
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... FUNCTIONAL DESCRIPTION 7.1 General Description The W83781D/G provides 5 analog positive inputs, 2 analog negative input, 3 fan speed monitors or fan ON/OFF control, 3 thermistor voltage inputs, case open detection and beep function output when the monitor value exceed the set limit value. When start the monitor function on the chip, the watch dog machine monitor every function and store the value to registers ...
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... The register structure is showed as the diagram next page. The second interface use Serial Bus. In the W83781D/G has three serial bus address. That is, the first address defined at CR48 can read/write all registers excluding Bank 1 and Bank 2 temperature 2/3 registers, the second address defined at CR4A.bit2-0 only read/write temperature sensor 2 registers, and the third address defined at CR4A ...
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... Serial Bus Write to Internal Address Register Only R Ack by 781D Internal Index Register Byte 0 (Continued R Ack by 781D Internal Index Register Byte R Ack by 781D Internal Index Register Byte W83781D/W83781G Ack by Frame 2 781D Ack Stop by by 781D Master Frame 3 Data Byte Ack Stop by by Master Frame 2 781D Ack Stop by by ...
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... Frame 2 by 781D MSB Data Byte R Ack by 781D ... ... Ack Frame 4 by 781D MSB Data Byte R Ack Frame 2 by 781D Data Byte - 9 - W83781D/W83781G , T ) HYST ... ... Ack Ack by Frame 3 by Master Master LSB Data Byte , HYST Ack Frame 2 by 781D Pointer Byte ... ... Ack No Ack ...
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... Ack Frame 1 by 781D R Ack by 781D MSB Data Byte R Ack by 781D 0 SCL (Cont...) SDA (Cont...) Frame 3 Configuration Data Byte Configuration Register Write - 10 - W83781D/W83781G Ack Frame 2 by 781D Pointer Byte Ack Stop by by Frame 4 Master Master Ack Frame 2 by 781D Pointer Byte ...
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... Ack by 781D Configuration Register Write +2.5VINA Positive Inputs +2.5VINB +3.3VIN R1 VDD(+5V) +12VIN Pin 31 -12VIN R2 Pin 30 -12VOUT R F -5VOUT Pin -5VIN Pin 28 10K, 1% VREF VTIN3 VTIN2 R THM VTIN1 - 11 - W83781D/W83781G Ack Frame 2 by 781D Pointer Byte Ack by Frame 4 781D LSB Data Byte Pin 36 ...
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... Ohms for -5V voltage input × 135 Count × RPM Divisor TIME PER COUNTS REVOLUTION 6.82 ms 153 13.64 ms 153 27.27 ms 153 54.54 ms 153 Publication Release Date: April 14, 2005 - 12 - W83781D/W83781G 70% RPM TIME FOR 70% 6160 9.74 ms 3080 19.48 ms 1540 38.96 ms 770 77.92 ms Revision 2.0 ...
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... Putput and Zener Clamp -complement for 9-Bit Digital Output 9-Bit Binary 9-Bit Hex 0,1111,1010 0FAh 0,0011,0010 032h 0,0000,0010 002h 0,0000,0001 001h 0,0000,0000 000h 1,1111,1111 1FFh 1,1111,1110 1FFh 1,1100,1110 1CEh 1,1001,0010 192h Publication Release Date: April 14, 2005 Revision 2.0 Pin 18/19/20 W83781D W83781D ...
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... The W83781D/G temperature interrupt has two mode: (1) The first is Interrupt Mode--exceeding T causes an interrupt until reset by reading Interrupt Status Register 1 (CR41). Once an interrupt event has occurred over T , the interrupt will occur again by the temperature going below T OI Comparator Mode--setting the T temperature exceeds T , the interrupt will be generate Interrupt ...
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... Bit7: Read Only The logical 1 indicates the device is busy because of a Serial Bus transaction or another ISA bus transaction. With checking this bit, multiple ISA drivers can use W83781D/G without interfering with each other or a Serial Bus driver the user's responsibility not to have a Serial Bus and ISA bus operations at the same time. ...
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... Publication Release Date: April 14, 2005 - 16 - W83781D/W83781G Notes Auto-increment to the address of SMI# Mask Register 2 after a read or write to Port x6h. Auto-increment to the address of IRQ Mask Register 2 after a read or write to Port x6h Revision 2.0 ...
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... Publication Release Date: April 14, 2005 - 17 - W83781D/W83781G Notes Auto-increment to the next location after a read or write to Port x6h and stop at 7Fh. Revision 2.0 ...
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... The logical 1 disables the SMI# and IRQ outputs without affecting the contents of Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit START EN_SMI# EN_IRQ INT_CLEAR RST_OUT# IRQPOL BEEP/GPO# INITIALIZATION - 18 - W83781D/W83781G Data Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Bit 3-0: The logical 1 indicates a High or Low limit has been exceeded. 8.5 Interrupt Status Register 2 – Index 42h (Bank 0) Register Location: 42h Power on Default Value 00h Attribute: Read Only Size: 8 bits W83781D/W83781G IN0 IN1 IN2 IN3 TEMP1 TEMP23 FAN1 FAN2 Publication Release Date: April 14, 2005 Revision 2.0 ...
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... SMI# Mask Register 2 – Index 44h (Bank 0) Register Location: 44h Power on Default Value 00h Attribute: Read/Write Size: 8 bits W83781D/W83781G IN4 -IN5 -IN6 FAN3 Case Open Reserved Reserved Reserved IN0 IN1 IN2 IN3 TEMP1 TEMP23 FAN1 FAN2 Publication Release Date: April 14, 2005 Revision 2.0 ...
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... IRQ Mask Register 2 – Index 46h (Bank 0) Register Location: 46h Power on Default Value <7:0> = 01000000 binary Attribute: Read/Write Size: 8 bits IN4 -IN5 -IN6 FAN3 Case Open Reserved Reserved RST_OUT# Enable V25INA V25INB V33IN V5IN VTHIN1 VTHIN23 FAN1 FAN2 - 21 - W83781D/W83781G Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Bit 3-0: The VID <3:0> inputs IN4 -IN5 -IN6 FAN3 Case Open Reserved Reserved Chassis Clear VID0 VID1 VID2 VID3 FAN1 RPM Control FAN1 RPM Control FAN2 RPM Control FAN2 RPM Control - 22 - W83781D/W83781G Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Note: This location stores the number of counts of the internal clock per revolution. FAN3 reading Note: This location stores the number of counts of the internal clock per revolution. IN0 High Limit, default value is defined by Vcore Voltage +0.2V W83781D/W83781G Serial Bus Address Reserved DESCRIPTION Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Note1 : For the high limits of the voltages, the device is doing a greater than comparison. For the low limits, however doing a less than or equal comparison. W83781D/W83781G DESCRIPTION IN0 Low Limit, default value is defined by Vcore Voltage - ...
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... Power on Default Value <7:1> is 000, 0001b <0> is mapped to VID <4> Size: 8 bits 7 Bit 7-1: Read Only - Device ID<6:0> Bit 0: Read/Write - The VID4 inputs/outputs. Reset by MR. Vcore 1 = Open or pull-up to Vin VID0 (VDC) VID4 VID3 W83781D/W83781G Processor Pins 0 = Connected to Vss VID2 VID1 VID0 VID4 DID< ...
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... Bit 2-0: Temperature 2 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits. Data SCL Interface SDA I2CADDR2 I2CADDR2 I2CADDR2 DIS_T2 I2CADDR3 I2CADDR3 I2CADDR3 DIS_T3 Configuration Pointer (Select Address Register W83781D/W83781G Register Temperature (Read Only) Register T Register HYST T Register OS Publication Release Date: April 14, 2005 Revision 2.0 ...
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... P2 P1 Index Register Selection (Bank1 & Bank2) Configuration (Read / Write) T (Read / Write) HYST T (Read / Write Reserved Reserved CLKINSEL CLKINSEL ADCOVSEL ADCOVSEL FAN3_DIV FAN3_DIV - 27 - W83781D/W83781G P0 CR50h & CR51h CR52h CR53h & CR54h CR55h & CR56h Publication Release Date: April 14, 2005 Revision 2.0 ...
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... FAN IN/OUT and BEEP/GPO# Control Register – Index 4Dh (Bank 0) Register Location: 4Dh Power on Default Value <7:0> 0001,0101. Reset by MR. Attribute: Read/Write Size: 8 bits Reserved IRQEDGE OVTPOL DIS_OVT1 DIS_OVT2 Reserved Reserved Reserved - 28 - W83781D/W83781G Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Register 50h ~ 5Fh Bank Select – Index 4Eh (No Auto Increase) (Bank 0) Register Location: 4Eh Power on Default Value <6:3> = Reserved, <7> <2:0> Reset by MR Attribute: Read/Write Size: 8 bits FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 GPOSEL DIS_ABN - 29 - W83781D/W83781G Publication Release Date: April 14, 2005 Revision 2.0 ...
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... RT_DATA Read/Write BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS VIDH VIDL R-T Table index port, which is mapped to data port 51h. The default value is 0x00. R-T Table data port, which is selected by RT_IDX W83781D/W83781G DESCRIPTION Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Enable BEEP Output from V-Core A if the monitor value exceed the limits value. Write 1, enable BEEP output. Default value is 0. 8.26 BEEP Control Register 2 – Index 57h (Bank Auto-increment) Register Location: 57h EN_V25A_BP EN_V25B_BP EN_V33_BP EN_V5_BP EN_T1_BP EN_T23_BP EN_FAN1_BP EN_FAN2_BP - 31 - W83781D/W83781G Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Bit 7: Winbond Chip ID number. Read this register will return 10h. 8.28 Temperature Sensor 2 Temperature Register – Index 50h (Bank 1) Register Location: 50h EN_V12_BP EN_NV12_BP EN_NV5_BP EN_FAN3_BP EN_CASO_BP Reserved Reserved EN_GBP W83781D/W83781G CHIPID Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Bit 7: Temperature <0> of sensor2, which is low byte. Bit 6-0: Reserved. This bit should be set to 0. 8.30 Temperature Sensor 2 Configuration Register – Index 52h (Bank 1) Register Location: 52h Power on Default Value <7:0> = 0x00 Size: 8 bits TEMP2<0> W83781D/W83781G TEMP2<8:1> Reserved Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. 8.32 Temperature Sensor 2 Hysteresis (Low Byte) Register – Index54h (Bank 1) Register Location: 54h Power on Default Value Attribute: Read Only Size: 8 bits STOP2 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved <7:0> = 0x0 - 34 - W83781D/W83781G THYST2<8:1> Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. 8.34 Temperature Sensor 2 Over-temperature (Low Byte) Register – Index 56h (Bank 1) Register Location: 56h Power on Default Value Size: 8 bits THYST2<0> <7:0> = 0x0 - 35 - W83781D/W83781G Reserved TOVF2<8:1> Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Bit 6-0: Read Only - Reserved. This bit should be set to 0. 8.35 Temperature Sensor 3 Temperature Register - Index 50h (Bank 2) Register Location: 50h Attribute: Read Only Size: 8 bits 7 6 Bit 7-0: Temperature <8:1> of sensor 2, which is high byte TOVF2<0> W83781D/W83781G Reserved TEMP2<8:1> Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Read/Write - Interrupt Mode select. This bit default is set to 0, which is Compared Mode. When set to 1, Interrupt Mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor TEMP2<0> STOP3 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved - 37 - W83781D/W83781G Reserved Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Bit 6-0: Reserved. This bit should be set to 0. 8.40 Temperature Sensor 3 over temperature (High Byte)Register – Index 55h (Bank 2) Register Location: 55h Power on Default Value <7:0> = 0x50 Attribute: Read/Write Size: 8 bits <7:0> = 0x0 THYST3<0> W83781D/W83781G THYST3<8:1> Reserved Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Temperature Sensor 3 Over-temperature (Low Byte) Register – Index 56h (Bank 2) Register Location: 56h Power on Default Value Size: 8 bits 7 6 Bit 7: Read/Write - Over-temperature bit 0, which is low Byte. Bit 6-0: Read Only - Reserved. This bit should be set <7:0> = 0x0 TOVF3<0> W83781D/W83781G TOVF3<8:1> Reserved Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Output High Voltage RATING -0.5 to 7 +70 -55 to +150 SYM. MIN. TYP. MAX +10 LIH I -10 LIL V 0.5 0.8 1 1.6 2.0 2 0 +10 LIH I -10 LIL W83781D/W83781G UNIT V V ° C ° C UNIT CONDITIONS μ μ μ μ -12 mA ...
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... Input High Threshold Voltage Hysteresis Input High Leakage Input Low Leakage SYM. MIN. TYP. MAX +10 LIH I -10 LIL V 0.5 0.8 1 1.6 2.0 2 0.5 1 +10 LIH I -10 LIL - 41 - W83781D/W83781G UNIT CONDITIONS μ μ μ μ Publication Release Date: April 14, 2005 Revision 2.0 ...
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... ISA Read/Write Interface Timing AEN SA[2:0],CS IOR# IOW# SD[7:0] IRQ AEN SA[2:0],CS# IOW# IOR# SD[7:0] IRQ VALID DATA t RVD t RDH t RI ISA Bus Read Timing VALID VALID DATA ISA Bus Write Timing - 42 - W83781D/W83781G t RCU VALID t WCU Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Read Cycle Update Read Strobe Width Read Data Hold Read Strobe to Clear IRQ Active Read to Valid Data Address Hold from Inactive Write Write Cycle Update Write Strobe to Clear IRQ Write Strobe Width Read Cycle = RCV Write Cycle = WCV W83781D/W83781G SYMBOL MIN. MAX ...
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... Serial Bus Timing PARAMETER SCL Clock Period Start Condition Hold Time Stop Condition Setup-up Time DATA to SCL Setup Time DATA to SCL Hold Time SCL and SDA Rise Time SCL and SDA Fall Time W83781D/W83781G t SCL t HD;DAT VALID DATA t SU;DAT Serial Bus Timing Diagram SYMBOL MIN ...
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... HOW TO READ THE TOP MARKING The top marking of W83781D W83781D 745AA Left: Winbond logo 1st line: Type number W83781D, D means LQFP (Thickness = 1.4 mm). 2nd line: Tracking code 745 : packages made in '97, week assembly house ID; A means ASE, O means OSE revision; A means version A, B means version B ...
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... PACKAGE DIMENTIONS (48-pin QFP See Detail F Seating Plane Detail W83781D/W83781G Dimension in inch Dimension in mm Symbol Nom. Nom. Min. Max. Min. A --- --- A 0.05 --- 1 A 1.35 1. 0.20 0.17 c --- 0.09 D 7.00 E 7.00 e 0. 0.45 0. --- 0. 3.5 Notes: 1. Dimensions D & not include interlead flash ...
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... APPLICATION CIRCUITS OF W83781D NOTE: 1. Selected CLKIN of 48M , 24M OR 14.318M 2. Pin OVT# connects with PIIX4 Pin THRM#(H19 there originally exists Pull-up Resistor on these lines, these resistors are not needed. 4. SMI# is connected to PIIX4 EXTSMI eliminate noise and to be VCC line, this line is as wider as better. ...
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... CASEOPEN SW U2B R21 2.2M 74HC14 CaseOpen Q' Q Switch open 1 0 normal state close W83781D does not reset (let Q=0), then stable open 0 1 open 1 0 after reset ps. 'Switch Open' means 'Case Close' CaseBlock VCC R24 100 LS1 SPEAKER BEEP/GPO# SpeakerBlock - 48 - W83781D/W83781G WINBOND ELECTRONICS CORP ...
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... April 14, 2005 W83781D/W83781G PAGE DESCRIPTION n.a. All the version before 0.60 are internal use. n.a. First published. 5 Pin 18-20: I/O Type → I/O Pin18-20:I/O Type → Fan 1, Pin18:Fan1→ 4 Fan3 5 Pin23: I/O Type → ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83781D/W83781G Important Notice Publication Release Date: April 14, 2005 - 50 - ...