CY7C1351F-117AC Cypress Semiconductor Corp, CY7C1351F-117AC Datasheet - Page 6

• Manufacturer Part Number: CY7C1351F-117AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1351F-117AC

• Density: 4.5Mb
• Access Time (max): 7.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 117MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 220mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05210 Rev. *B
Linear Burst Address Table (MODE = GND)
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
READ Cycle
(Begin Burst)
READ Cycle
(Continue Burst)
NOP/DUMMY READ
(Begin Burst)
DUMMY READ
(Continue Burst)
WRITE Cycle
(Begin Burst)
WRITE Cycle
(Continue Burst)
NOP/WRITE ABORT
(Begin Burst)
WRITE ABORT
(Continue Burst)
IGNORE CLOCK
EDGE (Stall)
SNOOZE MODE
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
2. X = Don’t Care.” H= Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
3. Write is defined by BW
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. The DQs and DQP
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
Address
Parameter
selects are asserted, see truth table for details.
OE is inactive or when the device is deselected, and DQs and DQP
A1, A0
First
00
01
10
11
Operation
[2, 3, 4, 5, 6, 7, 8 ]
[A:D]
Address
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to snooze current
ZZ inactive to exit snooze current
Second
A1, A0
[A:D]
01
10
11
00
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
, and WE. See truth table for Read/Write.
Address
External
External
External
Current
Used
None
None
None
None
None
None
Next
Next
Next
Next
Description
Address
A1, A0
Third
10
00
01
11
CE
H
X
X
X
X
X
L
X
L
X
L
L
X
X
1
CE
H
H
X
X
X
X
H
X
X
H
X
X
X
Address
L
Fourth
A1, A0
2
11
00
01
10
CE
H
X
X
X
L
X
L
X
L
X
L
X
X
X
[A:D]
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
3
= data when OE is active.
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
L
L
DD
DD
Interleaved Burst Address Table (MODE =
Floating or V
ADV/LD
Test Conditions
− 0.2V
− 0.2V
Address
A1, A0
H
H
H
H
H
X
X
L
L
L
L
L
L
L
First
00
01
10
11
WE
H
H
X
X
X
X
X
X
X
X
X
X
L
L
DD
Address
Second
A1, A0
BW
)
X
X
X
X
X
X
X
X
H
H
X
X
L
L
01
00
11
10
X
OE CEN
H
H
X
X
X
X
X
L
L
X
X
X
X
X
2t
Min.
CYC
0
Address
H
X
L
L
L
L
L
L
L
L
L
L
L
L
A1, A0
Third
10
00
01
11
L->H
L->H
L->H
L->H
L->H Data Out (Q)
L->H Data Out (Q)
L->H
L->H
L->H Data In (D)
L->H Data In (D)
L->H
L->H
L->H
CLK
CY7C1351F
2t
2t
X
Max.
[A:D]
40
CYC
CYC
= Three-state when
Three-state
Three-state
Three-state
Three-state
Three-state
Three-state
Three-state
Three-state
Three-state
Page 6 of 15
Address
Fourth
A1, A0
DQ
11
10
01
00
–
Unit
mA
ns
ns
ns
ns
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