CY7C1351F-117AC Cypress Semiconductor Corp, CY7C1351F-117AC Datasheet - Page 3

• Manufacturer Part Number: CY7C1351F-117AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1351F-117AC

• Density: 4.5Mb
• Access Time (max): 7.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 117MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 220mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05210 Rev. *B
Pin Configurations
Pin Definitions
A
BW
WE
ADV/LD
CLK
CE
CE
0
, A
1
2
Name
[A:D]
1
, A
37,36,32,33,34,
35,44,45,46,47,
48,49,50,81,82,
93,94,95,96
99,100
TQFP
88
85
89
98
97
(continued)
G
M
A
B
C
D
E
F
H
K
L
N
P
R
T
U
J
P4,N4,A2,C2,
R2,A3,B3,C3,
C5,T5,A6,C6,
T3,T4,A5,B5,
L5,G5,G3,L3
V
V
V
V
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
BGA
NC
NC
NC
NC
DDQ
DDQ
DDQ
DDQ
DDQ
1
R6
H4
B4
K4
E4
B2
C
C
C
C
D
D
D
D
DQP
DQP
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CE
V
NC
NC
2
A
A
A
DD
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-Clock
2
C
C
C
C
D
D
D
D
C
D
Input-
Input-
Input-
Input-
Input-
Input-
I/O
119-Ball BGA
MODE
BW
BW
V
V
V
V
V
V
V
V
V
NC
A
A
A
A
3
SS
SS
SS
SS
SS
SS
SS
SS
SS
C
D
Address Inputs used to select one of the 128K address lo-
cations. Sampled at the rising edge of the CLK. A
to the two-bit burst counter.
Byte Write Inputs, active LOW. Qualified with WE to conduct
writes to the SRAM. Sampled on the rising edge of CLK.
Write Enable Input, active LOW. Sampled on the rising edge
of CLK if CEN is active LOW. This signal must be asserted LOW
to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address
counter or load a new address. When HIGH (and CEN is as-
serted LOW) the internal burst counter is advanced. When
LOW, a new address can be loaded into the device for an ac-
cess. After being deselected, ADV/LD should be driven LOW in
order to load a new address.
Clock Input. Used to capture all synchronous inputs to the de-
vice. CLK is qualified with CEN. CLK is only recognized if CEN
is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge
of CLK. Used in conjunction with CE
lect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge
of CLK. Used in conjunction with CE
the device.
ADV/LD
CEN
CLK
V
CE
V
V
WE
NC
NC
OE
NC
NC
NC
A1
A0
A
4
DD
DD
DD
1
BW
BW
V
V
V
V
V
V
V
V
V
NC
NC
A
A
A
A
5
SS
SS
SS
SS
SS
SS
SS
SS
SS
A
B
DQP
DQP
Description
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CE
V
NC
NC
A
A
A
A
6
DD
3
B
B
B
B
A
A
A
A
B
A
1
V
V
V
V
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
and CE
2
NC
NC
NC
ZZ
DDQ
DDQ
DDQ
DDQ
DDQ
, and CE
7
B
B
B
B
A
A
A
A
CY7C1351F
3
to select/deselect
3
to select/dese-
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