CY62157DV18LL-70BVI Cypress Semiconductor Corp, CY62157DV18LL-70BVI Datasheet - Page 6

• Manufacturer Part Number: CY62157DV18LL-70BVI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62157DV18LL-70BVI

• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Document #: 38-05126 Rev. *B
Read Cycle No. 2 (OE Controlled)
Write Cycle No. 1 (WE Controlled)
Notes:
16. Address valid prior to or coincident with CE
17. Data I/O is high-impedance if OE = V
18. If CE
19. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
DATA OUT
DATA I/O
ADDRESS
CURRENT
ADDRESS
BHE
BHE /BLE
SUPPLY
CE 1
CE 2
WE
OE
CE
CE 2
1
/
V CC
OE
BLE
goes HIGH or CE
1
DON’T CARE
2
goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
HIGH IMPEDANCE
t
PU
(continued)
t
t
LZCE
SA
t
t
IH
HZOE
LZBE
.
[15, 16]
t
t
[13, 17, 18, 19]
ACE
LZOE
1
, BHE, BLE transition LOW and CE
50%
t
t
DOE
DBE
t
AW
t
SCE
t
RC
t
WC
t
BW
DATA
t
2
t
PWE
SD
transition HIGH.
IN
VALID
DATA VALID
t
HA
t
HZOE
t
HD
t
HZBE
t
HZCE
t
PD
50%
CY62157DV18
IMPEDANCE
Page 6 of 10
MoBL2
HIGH
I
I
CC
SB