CY62147DV30L-55ZSXI Cypress Semiconductor Corp, CY62147DV30L-55ZSXI Datasheet

CY62147DV30L-55ZSXI

Manufacturer Part Number
CY62147DV30L-55ZSXI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62147DV30L-55ZSXI

Density
4Mb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
2.5/3.3V
Address Bus
18b
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
15mA
Operating Supply Voltage (min)
2.2V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Word Size
16b
Number Of Words
256K
Lead Free Status / Rohs Status
Compliant
Cypress Semiconductor Corporation
Document #: 38-05340 Rev. *F
Features
Functional Description
The CY62147DV30 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
• Temperature Ranges
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62147CV25, CY62147CV30, and
• Ultra-low active power
• Ultra low standby power
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 48-ball VFBGA and
• Byte power-down feature
Logic Block Diagram
— Industrial: –40°C to +85°C
— Automotive-A: –40°C to +85°C
— Automotive-E: –40°C to +125°C
CY62147CV33
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 8 mA @ f = f
non Pb-free 44-pin TSOPII
Pow er
Circuit
A
A
A
A
A
A
A
A
A
A
A
10
6
5
4
3
2
1
0
9
8
7
[1]
-
Down
max
COLUMN DECODER
DATA IN DRIVERS
198 Champion Court
RAM Array
256K x 16
CE
BHE
BLE
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
mode reducing power consumption by more than 99% when
deselected (CE HIGH or both BLE and BHE are HIGH). The
input/output pins (I/O
pedance state when: deselected (CE HIGH), outputs are dis-
abled (OE HIGH), both Byte High Enable and Byte Low Enable
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62147DV30 is available in a 48-ball VFBGA, 44 Pin
TSOPII packages.
4-Mbit (256K x 16) Static RAM
17
San Jose
). If Byte High Enable (BHE) is LOW, then data
8
through I/O
,
0
CA 95134-1709
through I/O
0
I/O
I/O
to I/O
0
8
–I/O
–I/O
BHE
WE
CE
OE
BLE
7
7
15
. If Byte High Enable (BHE) is
15
0
Revised August 31, 2006
) is written into the location
through A
15
) are placed in a high-im-
CY62147DV30
0
17
through I/O
).
8
408-943-2600
®
to I/O
) in portable
15
. See
7
), is
0
[+] Feedback

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CY62147DV30L-55ZSXI Summary of contents

Page 1

... Down Circuit Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05340 Rev. *F 4-Mbit (256K x 16) Static RAM vanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL applications such as cellular telephones ...

Page 2

... Industrial CY62147DV30LL Industrial CY62147DV30L Auto-E CY62147DV30LL Industrial CY62147DV30LL Auto-A Notes pins are not internally connected on the die. 3. DNU pins have to be left floating or tied ensure proper application Pins H1, G2, and H6 in the VFBGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively. ...

Page 3

... Auto-A is available in –70 and Auto-E is available in –55. Document #: 38-05340 Rev. *F Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Device + 0.3V CC(MAX) CY62147DV30L + 0.3V CC(MAX) CY62147DV30LL + 0.3V CC(MAX) –45 Min. Typ 2.20V 2 2.70V 2 ...

Page 4

Capacitance (for all packages) Parameter Description C Input Capacitance IN C Output Capacitance OUT [10] Thermal Resistance Parameter Description Θ Thermal Resistance JA (Junction to Ambient) Θ Thermal Resistance JC (Junction to Case) AC Test Loads and Waveforms R1 ...

Page 5

Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid ACE t OE LOW to Data ...

Page 6

Switching Waveforms Read Cycle 1 (Address Transition Controlled) ADDRESS DATA OUT PREVIOUS DATA VALID [19, 20] Read Cycle No. 2 (OE Controlled) ADDRESS CE t ACE OE BHE/BLE t LZOE t DBE t LZBE HIGH IMPEDANCE DATA OUT t LZCE ...

Page 7

Switching Waveforms (continued) [17, 21, 22] Write Cycle No. 1 (WE Controlled) ADDRESS BHE/BLE OE 23 DATA I/O NOTE t HZOE [17, 21, 22] Write Cycle No. 2 (CE Controlled) ADDRESS CE WE BHE/BLE OE DATA ...

Page 8

Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS CE BHE/BLE NOTE 23 DATAI/O t Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) ADDRESS CE BHE/BLE DATA I/O NOTE 23 Document ...

Page 9

... VFBGA CY62147DV30LL-55BVXI CY62147DV30LL-55ZSXI 51-85087 44-pin TSOP II (Pb-free) CY62147DV30L-55BVXE 51-85150 48-ball (6 mm × 8mm × 1 mm) VFBGA (Pb-free) CY62147DV30L-55ZSXE 51-85087 44-pin TSOP II (Pb-free) 70 CY62147DV30LL-70BVI 51-85150 48-ball (6 mm × 8mm × 1 mm) VFBGA CY62147DV30LL-70BVXA Document #: 38-05340 Rev. *F ...

Page 10

Package Diagram TOP VIEW A1 CORNER 6.00±0.10 SEATING PLANE C Document #: 38-05340 Rev. *F 48-ball VFBGA ( mm) (51-85150) ...

Page 11

... Document #: 38-05340 Rev. *F © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 12

Document History Page Document Title:CY62147DV30 MoBL Document Number: 38-05340 Orig. of REV. ECN NO. Issue Date Change ** 127481 06/17/03 *A 131010 01/23/04 *B 213252 See ECN *C 257349 See ECN *D 316039 See ECN *E 330365 See ECN *F ...

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