CY7C1354BV25-200AC Cypress Semiconductor Corp, CY7C1354BV25-200AC Datasheet - Page 6

• Manufacturer Part Number: CY7C1354BV25-200AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354BV25-200AC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05292 Rev. *E
Pin Definitions
A0, A1, A
BW
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
DQ
DQP
DQP
MODE
TDO
TDI
TMS
TCK
V
V
DD
DDQ
1
2
3
a,
a,
a,
d
DQ
BW
Pin Name
DQP
b,
b,
DQ
BW
b,
DQP
c,
c,
DQ
BW
c
d
d
JTAG serial input
Test Mode Select
I/O Power Supply Power supply for the I/O circuitry.
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
Asynchronous
Power Supply
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
JTAG-Clock
JTAG serial
I/O Type
output
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Input-
Input-
Input-
Input-
I/O-
I/O-
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BW
DQ
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state and when the device has been
deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized
by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting
CEN does not deselect the device, CEN can be used to extend the previous cycle when
required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
The direction of the pins is controlled by OE and the internal control logic. When OE is
asserted LOW, the pins can behave as outputs. When HIGH, DQ
a three-state condition. The outputs are automatically three-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ
BW
burst order. Pulled LOW selects the linear burst order. MODE should not change states
during operation. When left floating MODE will default HIGH, to an interleaved burst
order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
This pin controls the Test Access Port state machine. Sampled on the rising edge
of TCK.
Clock input to the JTAG circuitry.
Power supply inputs to the core of the device.
b
[31:0]
b
, DQP
and DQP
. During write sequences, DQP
c
is controlled by BW
b
, BW
2
1
1
c
and CE
and CE
and CE
controls DQ
2
3
3
to select/deselect the device.
to select/deselect the device.
to select/deselect the device.
[17:0]
c
, and DQP
c
Pin Description
and DQP
during the previous clock rise of the read cycle.
a
is controlled by BW
d
c
is controlled by BW
, BW
a
controls DQ
d
controls DQ
CY7C1354BV25
CY7C1356BV25
a
a
and DQP
, DQP
d
d
a
.
and DQP
–DQ
b
is controlled by
a
d
, BW
are placed in
Page 6 of 27
d
b
.
controls