M28W640FST70ZA6 Micron Technology Inc, M28W640FST70ZA6 Datasheet - Page 22

• Manufacturer Part Number: M28W640FST70ZA6
• Manufacturer: Micron Technology Inc

Specifications of M28W640FST70ZA6

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 22b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 4M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Command Interface
6.7
6.8
6.9
22/76
Double Word Program command
This feature is offered to improve the programming throughput, writing a page of two
adjacent words in parallel.The two words must differ only for the address A0.
Three bus write cycles are necessary to issue the Double Word Program command:
Read operations output the Status Register content after the programming has started.
Programming aborts if Reset goes to V
program operation is aborted, the block containing the memory location must be erased and
reprogrammed.
See
flowchart for using the Double Word Program command.
Quadruple Word Program command
This feature is offered to improve the programming throughput, writing a page of four
adjacent words in parallel.The four words must differ only for the addresses A0 and A1.
A Quadruple word Program command will be ignored if V
Five bus write cycles are necessary to issue the Quadruple Word Program command:
Read operations output the Status Register content after the programming has started.
Programming aborts if Reset goes to V
program operation is aborted, the block containing the memory location must be erased and
reprogrammed.
See
flowchart for using the Quadruple Word Program command.
Clear Status Register command
The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status
Register to ‘0’. One bus write cycle is required to issue the Clear Status Register command.
The bits in the Status Register do not automatically return to ‘0’ when a new Program or
Erase command is issued. The error bits in the Status Register should be cleared before
attempting a new Program or Erase command.
Appendix
Appendix
The first bus cycle sets up the Double Word Program Command.
The second bus cycle latches the Address and the Data of the first word to be written.
The third bus cycle latches the Address and the Data of the second word to be written
and starts the Program/Erase Controller.
The first bus cycle sets up the Quadruple Word Program Command.
The second bus cycle latches the Address and the Data of the first word to be written.
The third bus cycle latches the Address and the Data of the second word to be written.
The fourth bus cycle latches the Address and the Data of the third word to be written.
The fifth bus cycle latches the Address and the Data of the fourth word to be written
and starts the Program/Erase Controller.
C,
C,
Figure 19: Double Word Program flowchart and pseudo code
Figure 20: Quadruple Word Program flowchart and pseudo
IL
IL
. As data integrity cannot be guaranteed when the
. As data integrity cannot be guaranteed when the
PP
is not set to V
M28WxxxFS, M28WxxxFSU
PPH
code, for the
.
for the