JL82575EB S LAAK Intel, JL82575EB S LAAK Datasheet

JL82575EB S LAAK

Manufacturer Part Number

JL82575EB S LAAK

Description

Manufacturer

Intel

Datasheet

1.JL82575EB_S_LAAK.pdf (4 pages)

Specifications of JL82575EB S LAAK

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Lead Free Status / Rohs Status

Compliant

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Product Brief

Intel® 82575EB Gigabit Ethernet Controller

Network Connectivity

Intel® 82575EB Gigabit Ethernet Controller

High-performance, Dual-Port Gigabit Network Connectivity for Server and Embedded

System Designs

• High-performing, PCI Express* 10/100/1000 Ethernet connection

• Dual-port, single-chip configuration simplifies designs

• Improves flexibility and performance in a virtualized environment

• Enhanced support for pass-through traffic to board management

The Intelligent Way to Connect

The Intel® 82575EB Gigabit Ethernet Controller is a single,

compact component with two fully integrated Gigabit Ethernet

Media Access Control (MAC) and physical layer (PHY) ports. This

device uses the PCI Express* 2.0 (2.5 Gbps) [x2 and x4] interface.

The Intel 82575EB Gigabit Ethernet Controller provides two IEEE

802.3* Ethernet interfaces for 1000BASE-T, 100BASE-TX, and

10BASE-T applications. Both ports also integrate a Serializer-

Deserializer (SerDes) interface to support 1000BASE-SX/LX

(optical fiber), Gigabit Ethernet backplane applications, and

external PHYs connected either on board or via SFP connectors

using SGMII signaling. Intel 82575EB Gigabit Ethernet Controller

provides hardware assists for auto sensing and switching

between copper and SerDes/SGMII interfaces.

High-Performance Design Features

The Intel 82575EB Gigabit Ethernet Controller for PCI Express

is designed for high performance and low memory latency. Wide

internal data paths eliminate performance bottlenecks by efficiently

handling large address and data words. The controller efficiently

handles packets with minimum latency by combining parallel and

pipelined logic architectures that are optimized for independent

transmit and receive queues. The controller includes advanced

interrupt-handling features, including MSI-X support and uses

efficient ring-buffer descriptor data structures with up to 64

packet descriptors per queue cached on chip. The controller also

allows efficient routing of packets to the target destination in a

virtualized environment using multiple hardware queues. Based

on the data type being transferred, the interrupts can be handled

either in an aggregation mode or sending interrupts immediately

upon receipt. A large 48 KByte per port on-chip packet buffer

maintains superior performance.

in multi-core systems by lowering interrupt overhead and provid-

ing sorted multiple data queue paths

controller

Direct Cache Access enables the I/O device to activate a pre-fetch

engine in the CPU that loads the data into the CPU cache ahead of

time, thereby eliminating cache misses and reducing CPU loads. In

addition, by using hardware acceleration, the controller can offload

certain tasks from the host such as transmit and receive checksum

calculations for Transmission Control Protocol (TCP), User Datagram

Protocol (UDP), and Internet Protocol (IP); header and data splitting of

received packets; and TCP segmentation of transmit packets.

Hardware-assisted Virtualization

As IT focuses on reducing costs by deploying virtualization and

consolidating servers, this new environment also creates unique

challenges for the I/O infrastructure. Recognizing these challenges,

Intel has designed smart acceleration capabilities into Ethernet Con-

trollers that optimizes networking performance on virtual servers.

The Intel 82575EB Gigabit Ethernet Controller adds Virtual Machine

Device queue (VMDq) technology that offloads data sorting and

data copying from the virtual machine monitor (VMM) software layer

to the hardware. This improves overall throughput and CPU utiliza-

tion on virtualized servers. VMDq technology also ensures transmit

fairness and prevents head-of-line blocking to deliver enhanced

latency performance.

Related parts for JL82575EB S LAAK

JL82575EB S LAAK Summary of contents

Page 1

... I/O infrastructure. Recognizing these challenges, Intel has designed smart acceleration capabilities into Ethernet Con- trollers that optimizes networking performance on virtual servers. The Intel 82575EB Gigabit Ethernet Controller adds Virtual Machine ...

Page 2

... MDIO register set. External PHYs can be controlled using either an IEEE 802.3 MDIO interface or using a 2-wire interface as defined in the SFP module specification. Both of the ports support the Wake on LAN feature. The Intel 82575EB Gigabit Ethernet Controller package mm, 576-pin Flip-Chip Ball Grid Array (FC-BGA). Benefits • Supports x4/x2 lanes • ...

Page 3

Features Host Offloading Features (continued) Tx/Rx IP, TCP, and UDP checksum offloading (IPv4, IPv6) capabilities Tx TCP segmentation offloading (IPv4, IPv6) IPv6 offloading Receive Side Scaling for Windows environment and Scalable I/O for Linux* environments (IPv4, IPv6, TCP/UDP) Advanced packet ...

Page 4

... Intel’s Web Site http://www.intel.com/. Copyright © 2007 Intel Corporation. All rights reserved. Intel, the Intel logo, Intel. Leap ahead., and the Intel. Leap ahead. logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. ...

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