S29GL128S10TFI010 Spansion Inc., S29GL128S10TFI010 Datasheet - Page 42

• Manufacturer Part Number: S29GL128S10TFI010
• Description: Flash 128 MBIT 3V 100NS PAGE MODE FLASH
• Manufacturer: Spansion Inc.

Specifications of S29GL128S10TFI010

• Data Bus Width: 16 bit
• Memory Type: Flash
• Memory Size: 128 Mbit
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: CFI
• Access Time: 100 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 100 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSOP-56
• Lead Free Status / Rohs Status: Compliant

42
5.4.3.4
5.4.3.5
DQ2: Toggle Bit II
Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is,
the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within the sector selected for erasure. (The system may
use either OE# or CE# to control the read cycles). But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in
Erase Suspend, but cannot distinguish if the sector is selected for erasure. Thus, both status bits are required
for sector and mode information. Refer to
Figure 5.5 on page 41
DQ2 on page 42
Figure 5.2 on page 30
Reading Toggle Bits DQ6/DQ2
Refer to
toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the previous value. If the toggle bit is not
toggling, the device has completed the program or erases operation. The system can read array data on
DQ15-DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is High (see
it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have
stopped toggling just as DQ5 went High. If the toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still toggling, the device did not complete the operation
successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone High. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of
Figure 5.5 on page 41
explains the algorithm. See also
shows the toggle bit algorithm in flowchart form, and the
shows the differences between DQ2 and DQ6 in graphical form.
D a t a
for the following discussion. Whenever the system initially begins reading
S h e e t
GL-S MirrorBit
Table 5.5 on page 44
Figure 5.6 on page
( A d v a n c e
®
Figure 5.6 on page 43
Family
DQ5: Exceeded Timing Limits on page
to compare outputs for DQ2 and DQ6.
I n f o r m a t i o n )
43).
S29GL_128S_01GS_00_01 February 11, 2011
shows the toggle bit timing diagram.
Reading Toggle Bits DQ6/
43). If