AD9882KST-140 Analog Devices Inc, AD9882KST-140 Datasheet - Page 25

• Manufacturer Part Number: AD9882KST-140
• Description: IC INTERFACE/DVI 100MHZ 100LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9882KST-140

• Rohs Status: RoHS non-compliant
• Applications: Video
• Interface: Analog, DVI
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount

Hexadecimal
Address
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
1
The AD9882A updates the PLL divide ratio only when the LSBs are written to Register 0x02.
Read and
Write or
Read Only
RO
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
Bit
7
6
5
4
3
2
7–0
7–0
7–0
7–0
7
6–0
7–1
0
7–0
7–0
Default
Value
0000 0000
0000 000X
0000 010X
0011 1111
1*** ****
*111 0000
0000 111*
**** ***1
Register Name
Active Hsync
Hsync Polarity
Detected
Active Vsync
Vsync Polarity
Detected
Coast Polarity
Detected
HDCP Keys
Detected
Test Register
Test Register
Test Register
Test Register
Test Register
Test Register
RXC Connect
Test Register
Test Register
MDA and MCL
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Function
0 = Hsync from the Hsync input pin.
1 = Hsync from the SOG input.
0 = Active low polarity detected.
1 = Active high polarity detected.
0 = Vsync from the Vsync input pin.
1 = Vsync from SOG.
0 = Active high polarity detected.
1 = Active low polarity detected.
0 = Active low polarity detected.
1 = Active high polarity detected.
This function works only with internal coast.
0 = Not detected.
1 = Detected.
Must be set to 1000 0000 for proper operation.
Must be set to 1100 000x for proper operation.
Must be set to 0111 110x for proper operation.
Must be set to default for proper operation.
0 = MDA and MCL three-stated.
1 = MDA and MCL not three-stated.
Must be set to *110 0111 for proper operation.
Must be set to default for proper operation.
0 = RX clock lines disconnected.
1 = RX clock lines connected.
Reserved for future use.
Reserved for future use.
AD9882A