AD9882KST-140 Analog Devices Inc, AD9882KST-140 Datasheet - Page 23

• Manufacturer Part Number: AD9882KST-140
• Description: IC INTERFACE/DVI 100MHZ 100LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9882KST-140

• Rohs Status: RoHS non-compliant
• Applications: Video
• Interface: Analog, DVI
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount

2-WIRE SERIAL REGISTER MAP
The AD9882A is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed
to write and read the control registers through the 2-wire serial interface port.
Table 12. Control Register Map
Hexadecimal
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
Read and
Write or
Read Only
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7–0
7–0
7–4
7–6
5–3
7–3
7–0
7–0
7–0
7–0
7–0
7–0
7–1
7–1
7–1
7–0
7–3
2
1
7
6
5
Default
Value
0110 1001
1101 ****
01** ****
**00 1***
1000 0***
0000 1000
0001 0100
0010 0000
1000 0000
1000 0000
1000 0000
1000 000*
1000 000*
1000 000*
0010 0000
0111 1***
**** *0**
**** **0*
0*** ****
*1** ****
**0* ****
Register Name
Chip Revisions
PLL Div MSB
PLL Div LSB
VCO Range
Charge Pump
Phase Adjust
Clamp Placement
Clamp Duration
Hsync Output
Pulse Width
Red Gain
Green Gain
Blue Gain
Red Offset
Green Offset
Blue Offset
Sync Separator
Threshold
Sync-on-Green
Threshold
Active Interface
Override
Active Interface
Select
Hsync Polarity
Override
Input Hsync
Polarity
Output Hsync
Polarity
Rev. 0 | Page 23 of 40
Function
An 8-bit register that represents the silicon level.
This register is for Bits [11:4] of the PLL divider. Larger values
mean the PLL operates at a faster rate. This register should be
loaded first whenever a change is needed. (This will give the PLL
more time to lock.)
Bits [3:0] LSBs of the PLL divider word. Links to PLL MSB to make
a 12-bit register.
Selects VCO frequency range.
Varies the current that drives the PLL loop filter.
ADC clock phase adjustment. Larger values mean more delay
(1 LSB = T/32).
Places the clamp signal an integer number of clock periods after
the trailing edge of Hsync.
Number of clock periods that the clamp signal is actively
clamping.
Sets the number of pixel clocks that HSOUT will remain active.
Controls the ADC input range (contrast) of the red channel.
Larger values give less contrast.
Controls the ADC input range (contrast) of the green channel.
Larger values give less contrast.
Controls the ADC input range (contrast) of the blue channel.
Larger values give less contrast.
Controls the dc offset (brightness) of the red channel.
Larger values decrease brightness.
Controls the dc offset (brightness) of the green channel.
Larger values decrease brightness.
Controls the dc offset (brightness) of the blue channel.
Larger values decrease brightness.
Sets how many pixel clocks to count before toggling high or low.
This should be set to some number greater than the maximum
Hsync or equalization pulsewidth.
Sets the voltage level of the sync-on-green slicer’s comparator.
0 = No override.
1 = User overrides, interface set by 0x0F, Bit 1.
0 = Analog interface active.
1 = Digital interface active.
This interface is selected only if Register 0x0F, Bit 2 is set to 1, or if
both interfaces are active.
0 = Polarity determined by chip.
1 = Polarity set by 0x10, Bit 6.
0 = Active low polarity.
1 = Active high polarity.
0 = Active high sync signal.
1 = Active low sync signal.
1
1
AD9882A