NCV3030ADR2G ON Semiconductor, NCV3030ADR2G Datasheet - Page 12

• Manufacturer Part Number: NCV3030ADR2G
• Description: IC PWM CTLR BUCK SYNC 8SOIC
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCV3030ADR2G

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.44MHz
• Duty Cycle: 84%
• Voltage - Supply: 4.7 V ~ 28 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CURRENT LIMIT AND CURRENT LIMIT SET
Overview
MOSFET during the on time to sense inductor current. The
Current Limit Set
sequence by forcing a typically 13 mA current through the
low side gate drive resistor. The gate drive output will rise
to a voltage level shown in the equation below:
Where I
on the low side MOSFET.
leakage from causing unwanted turn on of the low side
MOSFET. In this case, the resistor is also used to set the
I
process takes approximately 350 ms to complete prior to
Soft−Start stepping. The scaled voltage level across the I
resistor is converted to a 6 bit digital value and stored as the
trip value. The binary I
the analog I
The DAC has 63 steps in 6.51 mV increments equating to a
maximum sense voltage of 403 mV. During the I
Limit
CONTROL
The NCP3030 uses the voltage drop across the High Side
The I
This resistor is normally installed to prevent MOSFET
trip level reference through the I
Limit
SET
Limit
is 13 mA and R
comparator reference is set during the startup
reference voltage through a DAC counter.
6
V
Ilim Out
set
Limit
+ I
COUNTER
SET
value is scaled and converted to
DAC /
set
Itrip Ref−63 Steps, 6.51 mV/step
is the gate to source resistor
* R
set
Limit
Figure 25. I
DAC. The I
Switch
Cap
VSense
Itrip Ref
set
(eq. 1)
http://onsemi.com
period
set
SET
set
/ I
Limit
12
Vset
13 uA
Iset
Block Diagram
I
compares the differential voltage across the V
V
portion of the circuit is only active while the HS MOSFET
is turned ON.
prior to Soft−Start, the DAC counter increments the
reference on the I
voltage and holds the DAC reference output to that count
value. This voltage is translated to the I
during the I
switch cap circuit. See Figure 25. Exceeding the maximum
sense voltage results in no current limit. Steps 0 to 10 result
in an effective current limit of 0 mV.
Current Sense Cycle
to the switching cycle. Current level 1 in Figure 26
represents a condition that will not cause a fault. Current
level 2 represents a condition that will cause a fault. The
sense circuit is allowed to operate below the 3/4 point of a
given switching cycle. A given switching cycle’s 3/4 T
time is defined by the prior cycle’s T
10 ns steps. A fault occurs if the sensed MOSFET voltage
exceeds the DAC reference within the 3/4 time window of
the switching cycle.
Limit
SW
Figure 26 shows how the current is sampled as it relates
Pin with a resistor settable voltage reference. The sense
block consists of a voltage comparator circuit which
VCC
VSW
HSDR
LSDR
Sense
RSet
portion of the switching cycle through the
SET
comparator until it crosses the V
VIN
on
and is quantized in
Limit
CC
comparator
Pin and the
SET
on