LM4312SNX/NOPB National Semiconductor, LM4312SNX/NOPB Datasheet - Page 16

• Manufacturer Part Number: LM4312SNX/NOPB
• Description: IC MPL2 SERIALIZER 24B 48LLP
• Manufacturer: National Semiconductor

Specifications of LM4312SNX/NOPB

• Function: Serializer
• Data Rate: 900Mbps
• Input Type: Parallel
• Output Type: Serial
• Number Of Inputs: 24
• Number Of Outputs: 3
• Voltage - Supply: 1.6 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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SYSTEM CONSIDERATIONS
Typical VGA RGB888 Operation
A Smart Display application is shown in Figure 18. The Seri-
alizer (SER) resides by the host (BBP) and connects to a
Memory Interface. BBP Bus signals are connected as shown
(PCLK, Data, DE, PD*, VS, HS, and SPI signals). The device
can be configured for 18-bit or 24-bit RGB interfaces. RGB
signals are samples on the rising edge of the PCLK, and the
serial data lines use both edge of the serial clock. The SER
requires a pixel clock reference which is typically 25 MHz in
a VGA application. This signal is used to generate the serial
DC clock. The PCLK input is multiplied by the selected PLL
multiplier to determine the serial clock rate. In the 25 MHz
The DES VDD is set to be compatible with the Display(s) em-
ployed. Depending on application, the Mode24 and RDS may
be tie to high, low or connected to BBP (GPIO) pins. The PD*
should be tied to PD* pin on SER device. The other signals
DE, VS, and HS signals are outputs only. The connection be-
tween the DES device and the display(s) should be done such
that long stubs are avoided. The DES has user adjustable
edge rate controls for the parallel bus outputs. This can be
used to optimize the edge rate vs. the required VDD magni-
tude. This allows for using softer edges on the wide parallel
FIGURE 18. Typical VGA RGB888 Connection Diagram
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PCLK and 8X application, the DC rate will be 200 MHz. Due
to the serial transmission scheme using both clock edges, the
raw bandwidth is 400 Mbps per lane and device throughput
is 800 Mbps. Dither and LUT options are OFF by default and
can be turned ON by device SPI programming. The SER has
a SLEEP mode to save power when the display is not active.
The Sleep state is entered when the PD* signal is driven Low.
It is also entered if the PD* signal is High and the PCLK input
is stopped. When PCLK stop is used to place SER into Sleep
mode, the SPI registers and the LUT content are retained. In
the Sleep state, supply current into the SER is >1µA typical.
Several configuration pins are also required to be set. For a
SER, tie TM = L and RES1 = H. The DES recovers the serial
signals and generates the parallel bus for the Display.
data bus signals. The DES also provides a PE pin to flag any
parity errors detected. This signal maybe routed back to the
host for monitoring, or bought out to a test point. The DES
supports 18-bit for 24-bit mode. These modes are obtained
by setting the MODE24 pin to a logic Low for 18-bit mode or
to logic High for 24-bit mode. The Sleep state of the display
may be entered by driving the PD* signal to a logic Low. This
pin should be connected SED PD* pin. Several configuration
pins are also required to be set. For a DES, tie TM = L and
RES0 = L.
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