LM4312SNX/NOPB National Semiconductor, LM4312SNX/NOPB Datasheet - Page 15

• Manufacturer Part Number: LM4312SNX/NOPB
• Description: IC MPL2 SERIALIZER 24B 48LLP
• Manufacturer: National Semiconductor

Specifications of LM4312SNX/NOPB

• Function: Serializer
• Data Rate: 900Mbps
• Input Type: Parallel
• Output Type: Serial
• Number Of Inputs: 24
• Number Of Outputs: 3
• Voltage - Supply: 1.6 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LM4312 Operation
POWER SUPPLY & BYPASS RECOMMENDATION
The V
gether to the same plane.
Bypass capacitors should be placed near the power supply
pins of the device. Use high frequency ceramic (surface
mount recommended) 0.1 µF capacitors. A 2.2 to 4.7 µF Tan-
talum capacitor is recommended near the SER for PLL by-
pass. Connect bypass capacitors with wide traces and use
dual or larger via to reduce resistance and inductance of the
feeds. Utilizing a thin spacing between power and ground
planes will provide good high frequency bypass above the
frequency range where most typical surface mount capacitors
are less effective. To gain the maximum benefit from this, low
inductance feed points are important. Also, adjacent signal
layers can be filled to create additional capacitance. Minimize
loops in the ground returns also for improved signal fidelity
and lowest emissions.
UNUSED INPUT PINS
Unused inputs must be tied to the proper input level — do not
float.
PHASE-LOCKED LOOP
A PLL is enabled to generate the serial link clock. The Phase-
locked loop system generates the serial data clock at 6 or 8
of the input clock depending upon 18 or 24-bit RGB transport
mode (set by SPI Register).
SLEEP MODE & STOP CLOCK
The LM4312 (SER) can eneter SLEEP (Low Power state) by
two methods. The PD* pin is one method, the other is by
stopping the PCLK input (to a static level).
The PD* Input pin may be controlled by the Host. When PD*
= High, the SER is enabled. When the PD* = Low, the SER
is in SLEEP Mode. Note that SPI Registers are reset to defult
values, and LUT data is retained.
When using the auto power down mode, the PD* input needs
to be held High. When the PCLK is held static, the SER will
detect this condition and power down. When the PCLK is
restarted, the SER powers up. See Figures 3, 4 and Figure
8. The stopping of the pixel clock should be done cleanly. The
minimum clock stop gap should be at least 4 PCLK cycles
wide. Floating of the PCLK input pin is not recommended.
Consult the MPL-2 DES datasheet to determine requirements
that the DES requires. When the SER is in SLEEP by the
DD
power supply pins are intended to be connected to-
15
STOP CLOCK feature, SPI Register and LUT contents are
retained.
If power is removed from the device, SPI Register and LUT
contents are reset upon power up.
Application Information
SYSTEM BANDWIDTH CALCULATIONS
For a HVGA (320 X 480) application with the following as-
sumptions: 60 Hz refresh rate, 10% blanking, RGB666, the
following calculations can be made:
Calculate PCLK - 320 X 480 X 1.1 X 60 = 10.14 MHz PCLK
Calculate DC rate - since the application is 2 DD + DC and
RGB666, PCLK X 6 is the DC rate or 60.83 MHz. Also check
that this DC rate does not exceed the DC maximum rate for
the chipset.
Calculate DD rate - MPL-2 uses both edges of the DC to send
serialized data, thus data rate is 2X the DC rate, or 121.7
Mbps per DD lane in our example.
Calculate the application throughput - using 2 DD lanes,
throughput is 2 X of the DD rate or 243.3 Mbps of raw band
width.
For a VGA (640 X 480) application with the following assump-
tions: 60 Hz refresh rate, 35% blanking, RGB888, the follow-
ing calculations can be made:
Calculate PCLK - 640 X 480 X 1.35 X 60 = 24.88 MHz PCLK
Calculate DC rate - since the application is 2 DD + DC and
RGB888, PCLK X 8 is the DC rate or ~ 200 MHz.
Calculate DD rate - MPL-2 uses both edges of the DC to send
serialized data, thus data rate is 2X the DC rate, or 400 Mbps
per DD lane in our example.
Calculate the application throughput - using 2 DD lanes,
throughput is 2X of the DD rate or 800 Mbps of raw band
width.
Mode
Power Cycle
VDDs = 0V
Sleep State
PD* = L
Sleep State
PD* = H and PCLK =
static (H or L)
LM4312 Memory Status (LUT and SPI Registers)
LUT
LUT contents are
reset
LUT contents
retained
LUT contents
retained
SPI Registers
Registers RESET
to Defaults
Registers RESET
to Defaults
Register contents
retained
www.national.com