LM4312SNX/NOPB National Semiconductor, LM4312SNX/NOPB Datasheet
LM4312SNX/NOPB
Specifications of LM4312SNX/NOPB
Related parts for LM4312SNX/NOPB
LM4312SNX/NOPB Summary of contents
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... Typical Application Diagram - Bridge Chips - 24-bit to 18-bit RGB Ordering Information NSID Package Type LM4312 48L LLP, 6mm x 6mm x 0.4mm, 0.4mm pitch © 2008 National Semiconductor Corporation Features ■ RGB Display Interface to >640 x 480 (VGA) Resolution ■ 18-bit RGB Transport ■ ...
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Pin Descriptions No. Pin Name of Pins MPL-2 SERIAL BUS PINS DD0P, DD0M, 4 DD1P, DD1M DCP, DCM 2 SPI INTERFACE and CONFIGURATION PINS SPI_CSX 1 SPI_SCL 1 SPI_DI 1 SPI_DO 1 PD* 1 RES1 VIDEO INTERFACE ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS Input/Output Voltage MPL-2 Output Voltage Junction Temperature Storage Temperature ESD Ratings: HBM, 1.5 kΩ, 100 pF EIAJ, 0Ω, 200 pF Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified ...
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Symbol Parameter SUPPLY CURRENT I Total Supply Current - DD RGB24 Mode. (Note 4) Total Supply Current - RGB18 Mode. I Supply Current—Disable DDZ Power Down Modes PD Power Dissipation Switching Characteristics Over recommended operating supply and temperature ranges unless ...
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Recommended Input Timing Requirements (PCLK and SPI) Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter PIXEL CLOCK (PCLK) f Pixel Clock Frequency PCLK PCLK Pixel Clock Duty Cycle DC t Input Transition Time T ...
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Timing Diagrams www.national.com FIGURE 1. Input Timing for RGB Interface FIGURE 2. Serial Data Valid FIGURE 3. Stop Pixel Clock (PCLK) Power Down FIGURE 4. Stop Pixel Clock (PCLK) Power Up 6 30011626 30011616 30011629 30011630 ...
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Functional Description The LM4312 is a Mobile Pixel Link two Serializer that serial- izes a 24-bit RGB plus three control signals (VS, HS, and DE) to two MPL-2 DD lines plus the serial clock DC line. 18-bit RGB, 24-bit RGB, ...
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BUS OVERVIEW The LM4312 is a multi-lane MPL-2 Serializer that supports an 18-bit or 24-bit RGB source interface. The MPL-2 physical layer is purpose-built for robustness, low power and low EMI data transmission while requiring the fewest number of signal ...
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RGB VIDEO INTERFACE The LM4312 is transparent to data format and control signal polarity timing. Each PCLK, RGB inputs, HS, VS and DE are sampled on the rising edge of the PCLK. A PCLK by PCLK representation of these signals ...
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This pro- cess has a "blue noise" characteristic that minimizes the visibility of the dither patterns. The resulting data stream of 18-bit data is then serialized and transmitted via MPL-2. The Dither circuitry requires ...
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PAGE WRITE The PAGE WRITE is shown in Figure 16. The SPI_DI payload consists of a "0" (Write Command), seven address bits of the start address and then the consecutive data bytes. 256 bytes maximum can be sent. The SPI_CSX ...
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LM4312 SPI Registers Name Address Command 0x00 Reserved, (Note 15) 0x01 LUT Red RAM 0x02 Address LUT Red RAM Data 0x03 LUT Green RAM 0x04 Address LUT Green RAM 0x05 Data LUT Blue RAM 0x06 Address LUT Blue RAM Data ...
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Note 13 WRITE is done to a reserved bits, data should be all 0’ READ is done to a reserved location, either 1’s or 0’s may be returned. Mask reserved data bits. Note 14: This register ...
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In Figure 17, 33 host signals are reduced to only signals. The reduced width interface to the display includes: 3 differential signals (DD0, DC, DD1), a Display Driver Reset signal (RSTN) and wire SPI ...
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LM4312 Operation POWER SUPPLY & BYPASS RECOMMENDATION The V power supply pins are intended to be connected to- DD gether to the same plane. Bypass capacitors should be placed near the power supply pins of the device. Use high frequency ...
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SYSTEM CONSIDERATIONS Typical VGA RGB888 Operation A Smart Display application is shown in Figure 18. The Seri- alizer (SER) resides by the host (BBP) and connects to a Memory Interface. BBP Bus signals are connected as shown (PCLK, Data, DE, ...
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FLEX CIRCUIT RECOMMENDATIONS The MPL-2 lines should generally run together to minimize any trace length differences (skew). For impedance control and also noise isolation (crosstalk), guard ground traces are recommended in between the signals. Commonly a Ground- Signal-Signal-Ground (GSSGSSG) layout ...
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Connection Diagram 48L LLP Package www.national.com TOP VIEW (not to scale) 18 30011619 ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48L LLP, 0.4mm pitch Order Number LM4312SM NS Package Number SNF48A 19 www.national.com ...
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