MC33793DR2 Freescale Semiconductor, MC33793DR2 Datasheet - Page 23

• Manufacturer Part Number: MC33793DR2
• Description: IC DSI SLAVE FOR R-SENSE 16-SOIC
• Manufacturer: Freescale Semiconductor
• Type: Distributed Systems Interfacer

Specifications of MC33793DR2

• Input Type: Logic
• Output Type: Logic
• Interface: 2 Line, I²C (CLK, Address/Data)
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: MC33793DR2TR

both the master and slave devices will read bad data. The
slave reacts to bad data by not sending a response during the
next frame. The master will detect a CRC error once it
receives the corrupted data sent by the slave, and once again
when the slave fails to respond. This is illustrated in
When this error occurs, the system software needs to
acknowledge this condition and resend a command (any
command of same size) so that it can receive the previous
POWER UP RESET
must allow enough time for the internal 5.0 volt regulator of
each device to come up to a proper level. This implies that
H_CAP must charge up to
6.0 volts. The time this takes is a function of the size of
H_CAP, and the current drive of the Master. The following
equation can be used to estimate the minimum time to wait
before sending an Initialization Command:
where I
Master.
and enough time must be allowed for all down-stream
devices in the chain to charge up. For example, if device #1
has it’s switch closed after its Initialization Command, then
the system must wait for device #2 to power up before
sending its Initialization Command, and so on down the line.
bus configuration, then the total capacitor value is the sum of
all H_CAPS.
allocated for the bus fault test (see next section).
BUS FAULTS
“Inactive Side” of the Bus Switch that is greater than 3V
(typical). Inactive refers to the side of the bus that is not yet
connected to the bus. Just before a device is Forward
Initialized, the inactive side is defined as BUSOUT. Similarly,
Analog Integrated Circuit Device Data
Freescale Semiconductor
Master
Slave
If there is a bus error (due to induced noise or a bus fault),
When power is first applied to the DSI bus, the system
t
The above assumes a daisy-chain type of bus topology,
If the devices are attached in a parallel or point-to-point
In addition to the charge up time, enough time must be
A bus fault is defined as an external voltage on the
MIN
≅ (H_CAP x 6V) / I
CHARGE
Command N
Response N-1
is the charging current provided by the DSI
Bus Error
Figure 7. Bus Traffic With Receive Errors (Master Reads Incorrect Data)
CHARGE
V
RECT
+ 5.0 V, or approximately
Command N+1
Response N
Error
CRC
Figure
CRC
Error
Command N+2
No Response
7.
response just prior to the bus fault condition (in this case,
Command N).
errors as shown in
Responses N+1 and N+2 and will mistake them for N+3 and
N+4. The master should send another N+1 command after
the error is acknowledged to re-synchronize the command-
response sequence.
just before a device is Reverse Initialized, the BUSIN is
defined as the inactive side.
Forward or Reverse Initialization (when BS bit is set) by
applying an 11 mA pull-down current to the inactive side of
the Bus Switch and monitoring the voltage. The fault test
takes approximately 200 μS. If no fault is detected, the bus
switch will be closed, and if a fault is detected, the bus switch
will not close. The fault test applies to both programmed and
unprogrammed devices.
the last device BUSOUT line connects to BUSIN of the first
device (loop-back), then the fault test will NOT be executed
since both BUSIN and BUSOUT are connected to active
busses. It is up to the system software to run the appropriate
diagnostic tests to resolve this special case. (One alternative
is to use a separate DSI Master to handle the loop-back
signal path. This second DSI Master is only activated in the
case of a bus fault so that the last device can be accessed by
means of a reverse initialization.)
GLOBAL ADDRESS 0
command is sent to the 33793 with an address of 0x0 (global
address), the device behaves as follows:
Failure to take corrective action will result in unintended
The test for a bus fault is only performed once during
Exception: In the case of a daisy-chain bus topology where
Any time an Initialization or Reverse Initialization
• Device initializes to address 0.
• Bus switch remains open. This implies that in a daisy-
• NV and BS bits are not stored and have no effect.
CRC
Error
chain bus topology, all devices past the first device will
remain off.
Command N+3
Response N
Figure
Data misinterpreted by Master
7. In this case, the master will miss
Command N+4
Response N+3
TYPICAL APPLICATIONS
33793
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