DS4550E+T&R Maxim Integrated Products, DS4550E+T&R Datasheet - Page 14

• Manufacturer Part Number: DS4550E+T&R
• Description: IC I/O EXPANDER I2C 9B 20TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS4550E+T&R

• Interface: I²C
• Number Of I /o: 9
• Interrupt Output: No
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Includes: EEPROM, JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
Expander Plus Memory
The following terminology is commonly used to
describe I
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, start and stop conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
Start Condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See the timing dia-
gram for applicable timing.
Table
14
EEPROM
EEPROM
2
Address
Register
Address
Register
Select
Select
STEP
Load
Write
Write
Data
C and JTAG Nonvolatile 9-Bit I/O
I
____________________________________________________________________
2
C Serial Interface Description
5. EEPROM Write Cycle
2
C data transfers.
Select-IR-Scan
Capture-IR
Shift-IR (4 x TCK)
Exit1-IR
Update-IR
Select-DR-Scan
Capture-DR
Shift-DR (8 x TCK)
Exit1-DR
Update-DR
Select-IR-Scan
Capture-IR
Shift-IR (4 x TCK)
Exit1-IR
Update-IR
Select-DR-Scan
Capture-DR
Shift-DR (8 x TCK)
Exit1-DR
Update-DR
TAP STATE
I
2
C Definitions


The 4-bit instruction is shifted in through TDI.



No-op.
The 8-bit address is shifted in through TDI.

The shifted 8-bit Address Register data is output latched.


The 4-bit instruction is shifted in through TDI.



No-op.
The 8-bit data is shifted in through TDI.

The shifted 8-bit EEPROM Write Register data is output latched and written to the
EEPROM.
Stop Condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high gener-
ates a stop condition. See the timing diagram for
applicable timing.
Repeated Start Condition: The master can use a
repeated start condition at the end of one data transfer to
indicate that it will immediately initiate a new data trans-
fer following the current one. Repeated starts are com-
monly used during read operations to identify a specific
memory address to begin a data transfer. A repeated
start condition is issued identically to a normal start con-
dition. See the timing diagram for applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold-time requirements (see
shifted into the device during the rising edge of the SCL.
COMMENTS
Figure
5). Data is