STMPE2401TBR STMicroelectronics, STMPE2401TBR Datasheet - Page 15

IC I/O EXPANDER I2C 24B 36TFBGA

STMPE2401TBR

Manufacturer Part Number
STMPE2401TBR
Description
IC I/O EXPANDER I2C 24B 36TFBGA
Manufacturer
STMicroelectronics
Datasheet

Specifications of STMPE2401TBR

Interface
I²C
Number Of I /o
24
Interrupt Output
Yes
Frequency - Clock
400kHz
Voltage - Supply
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
36-TFBGA
Includes
Keypad, POR, PWM
For Use With
497-6426 - BOARD EVAL BASED ON STMPE2401
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-6133-2

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STMPE2401
6.4
6.5
6.6
Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
Slave device address
The slave device address is a 7 address, where the least significant 2-bit are programmable.
These 2-bit values will be loaded in once upon reset and after that these 2 pins no longer be
needed with the exception during General Call. Up to 4 STMPE2401 devices can be
connected on a single I
Table 12. Slave device address
Memory addressing
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and followed by the slave device address. Accompanying the slave device
address, there is a Read/Write bit (R/W). The bit is set to 1 for Read and 0 for Write
operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledgement on the SDA during the 9
from the bus by not responding to the transaction.
ADDR 1
0
0
1
1
2
C bus.
ADDR 0
0
1
0
1
th
bit time. If there is no match, it deselects itself
Address
0x8A
0x84
0x86
0x88
I2C Interface
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