STMPE801QTR STMicroelectronics, STMPE801QTR Datasheet
STMPE801QTR
Specifications of STMPE801QTR
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STMPE801QTR Summary of contents
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... Portable media player, Game console ■ Mobile phone, Smart phone Table 1. Device summary Order codes STMPE801QTR STMPE801MTR July 2007 Description The STMPE801 is a GPIO (General Purpose Input / Output) port expander able to interface a main digital ASIC via the two-line bidirectional bus ...
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Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STMPE801 7 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Block diagram 1 Block diagram Figure 1. Block diagram 4/26 STMPE801 ...
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STMPE801 2 Pin settings 2.1 Pin connection Figure 2. Pin connection QFN16L Top View Top View ...
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Pin settings 2.2 Pin assignment Table 2. Pin assignment Pin N° SO-16 QFN16L 6/26 Name 1 INT INT output 2 Reset Reset Input (Active ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 3.1 Absolute maximum rating Table 3 ...
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Electrical specification 4 Electrical specification 4.1 DC electrical characteristics Table 5. DC electrical characteristics Symbol Parameter V Core supply voltage supplì voltage IO Ipd Power down current Operating current Icc Max (No peripheral activity) Icc Operating current ...
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STMPE801 module STMPE801 is interface to the main processor using an I2C bus address Addressing scheme of STMPE801 is designed to allow devices to be connected to 2 the ...
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I2C module 2 Figure timing 2 Table address Symbol f SCL clock frequency SCL t Clock low period LOW t Clock high period HIGH t SDA and SCL fall time F START condition hold ...
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STMPE801 5.3 Start condition A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state. A Start condition must precede any data/command transfer. The device continuously monitors for a Start condition and will ...
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I2C module 5.7 Operation modes Table 8. Operation modes Mode Bytes Read Write Figure 5. Read and write modes (random and sequential) One Byte Read More than One Byte Read One Byte Write More than One Byte Write 12/26 Programming ...
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STMPE801 5.8 Read operation A write is first performed to load the register address into the Address Counter but without sending a Stop condition. Then, the bus master sends a reStart condition and repeats the Device Address with the R/W ...
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Turning I2C block OFF and ON 5.11 General call A general call address is a transaction with the slave address of 0x00 and R When a general call address is made, the device responds to this transaction with ...
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STMPE801 7 Register map Table 10. Register map Address 0x00 0x02 0x04 0x08 0x09 0x10 0x11 0x12 7.1 System and identification registers Table 11. System and identification registers Register name Chip ID Version ID Systemcontrol 7.2 System control register Table ...
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Interrupt, power supply & reset 8 Interrupt, power supply & reset STMPE801 could be configured to generate an interrupt when there is a logic transition of any of the GPIO configured as input. 8.1 Interrupt enable GPIO mask register (IEGPIOR) ...
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STMPE801 8.2 Interrupt status GPIO register (ISGPIOR) ISGPIOR register monitors the status of the interruption from a particular GPIO pin interrupt source to the host. Regardless whether the IEGPIOR bits are enabled or not, the ISGPIOR bits are still updated. ...
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Interrupt, power supply & reset All GPIO registers are named as GPxx, where Xxx represents the functional group Bit GPxx The function of each bit is shown in the following table: Table 16. Pin function Register Name GPIO Monitor Pin ...
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STMPE801 9 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on ...
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Package mechanical data Table 17. QFN16L mechanical data Dim Figure 6. Package dimensions 20/26 mm. Min Typ Max 0.45 0.55 0.60 0.02 0.05 0.15 0.20 0.25 2.50 2.60 2.70 1.70 1.80 1.90 0.40 ...
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STMPE801 Figure 7. Footprint recommendation Figure 8. Marking Device Marking (525) B: Dot Package mechanical data 21/26 ...
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Package mechanical data Figure 9. QFN16L tape and reel information 22/26 STMPE801 ...
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STMPE801 Figure 10. QFN16L tape and reel information (continued) Package mechanical data 23/26 ...
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Package mechanical data Table 18. SO-16 mechanical data Dim Figure 11. Package dimensions 24/26 mm. Min. Typ Max. 1.75 0.1 0.25 1.64 0.35 0.46 ...
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STMPE801 10 Revision history Table 19. Revision history Date 07-Dec-2006 22-Jan-2007 27-Apr-2007 02-Jul-2007 Revision 1 Initial release 2 Added Marking and Reel information 3 Updated Chapter 8.4 4 Coverpage QFN package drawing updated Revision history Changes and Chapter 8.5 on ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...