PIC18F6585-I/PT Microchip Technology Inc., PIC18F6585-I/PT Datasheet - Page 287

• Manufacturer Part Number: PIC18F6585-I/PT
• Description: 64 PIN, 48 KB FLASH, 3328 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6585-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 48K Bytes
• Ram Size: 3.3K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

23.2.2
This section describes the dedicated CAN Transmit
Buffer registers and their associated control registers.
REGISTER 23-5:
 2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Mode 1, 2
DEDICATED CAN TRANSMIT
BUFFER REGISTERS
Mode 0
TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS [0
bit 7
Legend:
C = Clearable bit
‘1’ = Bit is set
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
TXBIF: Transmit Buffer Interrupt Flag bit
1 = Transmit buffer has completed transmission of message and may be reloaded
0 = Transmit buffer has not completed transmission of a message
TXABT: Transmission Aborted Status bit
1 = Message was aborted
0 = Message was not aborted
TXLARB: Transmission Lost Arbitration Status bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit
1 = Requests sending a message. Clears the TXABT, TXLARB, and TXERR bits.
0 = Automatically cleared when the message is successfully sent
Unimplemented: Read as ‘0’
TXPRI1:TXPRI0: Transmit Priority bits
11 = Priority Level 3 (highest priority)
10 = Priority Level 2
01 = Priority Level 1
00 = Priority Level 0 (lowest priority)
TXBIF
R/C-0
Note:
Note 1: This bit is automatically cleared when TXREQ is set.
U-0
—
2: While TXREQ is set, Transmit Buffer registers remain read-only.
3: These bits define the order in which transmit buffers will be transferred. They do not
Clearing this bit in software while the bit is set, will request a message abort.
alter the CAN message identifier.
TXABT
TXABT
R-0
R-0
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
R = Readable bit
PIC18F6585/8585/6680/8680
TXLARB
TXLARB
R-0
R-0
(2)
TXERR
TXERR
(3)
R-0
R-0
W = Writable bit
(1)
(1)
TXREQ
TXREQ
R/W-0
R/W-0
(1)
x = Bit is unknown
- n = Value at POR
U-0
U-0
—
—
TXPRI1
TXPRI1
n
R/W-0
R/W-0
DS30491C-page 285
2]
TXPRI0
TXPRI0
R/W-0
R/W-0
bit 0