PIC18F6585-I/PT Microchip Technology Inc., PIC18F6585-I/PT Datasheet - Page 248

• Manufacturer Part Number: PIC18F6585-I/PT
• Description: 64 PIN, 48 KB FLASH, 3328 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6585-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 48K Bytes
• Ram Size: 3.3K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F6585/8585/6680/8680
18.3.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RC7/RX/DT pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a synchronous master reception:
1.
2.
FIGURE 18-12:
TABLE 18-8:
DS30491C-page 246
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend:
RC7/RX/DT pin
RC7/TX/CK pin
RC7/TX/CK pin
Name
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Note:
(SCKP = 0)
(SCKP = 1)
(Interrupt)
CREN bit
bit SREN
SREN bit
RCIF bit
RXREG
Write to
Read
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
USART Receive Register
Baud Rate Generator Register, High Byte
Baud Rate Generator Register, Low Byte
USART SYNCHRONOUS MASTER
RECEPTION
GIE/GIEH PEIE/GIEL TMR0IE
PSPIF
PSPIE
PSPIP
SPEN
CSRC
Bit 7
Q2
—
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
bit 0
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
INT0IE
CREN
SYNC
SCKP
Bit 4
TXIF
TXIE
TXIP
bit 2
ADDEN
SENDB
BRG16
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
bit 3
TMR0IF
CCP1IF
CCP1IE
CCP1IP
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
BRGH
FERR
Bit 2
—
Ensure bits CREN and SREN are clear.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit 4
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
Bit 1
bit 5
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
Bit 0
RBIF
bit 6
 2004 Microchip Technology Inc.
0000 0000
0000 0000
0000 0000
1111 1111
0000 000x
0000 0000
0000 0010
-1-0 0-00
0000 0000
0000 0000
POR, BOR
Value on
bit 7
Q1 Q2 Q3 Q4
0000 0000
0000 0000
0000 0000
1111 1111
0000 000x
0000 0000
0000 0010
-1-0 0-00
0000 0000
0000 0000
Value on
all other
Resets
‘0’