PEB24902HV2.1XT Infineon Technologies, PEB24902HV2.1XT Datasheet - Page 35

• Manufacturer Part Number: PEB24902HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEB24902HV2.1XT

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Compliant

3.6
The IEC-4-AFE-X Version 3.2 provides a boundary scan support for a cost effective
board testing. It consists of:
•
•
•
•
•
Boundary Scan
The following pins are included in the boundary scan:
#27 DIN, #7 CL15, #26 CLOCK, #23 CODE, #38 PDM0, #39 PDM1, #40 PDM2, #8
PDM3, # 25 RES, #41 SDR, #24 SDX
Former N.C. pins: #12 SCS, #43 SCLK, #54 DOUT, #35 ADDR0, #14 ADDR1, and #45
ADDR2 are not included into boundary scan.
Depending on the pin functionality one, two or three boundary scan cells are provided.
Table 13
Pin Type
Input
Output
I/O
When the TAP controller is in the appropriate mode data is shifted into or out of the
boundary scan via the pins TDI/TDO using the 6.25 MHz clock on pin TCK.
Table 14
Boundary Scan
Number
TDI ––>
1
2
3
4
5
Data Sheet
Complete boundary scan for 11 signals (pins) according to IEEE Std. 1149.1
specification.
Test access port controller (TAP)
Four dedicated pins (TCK, TMS, TDI, TDO)
One 32-bit IDCODE register
Pin TDISS tied to low disables the complete Boundary Scan Test Controller
Boundary Scan Test Controller
Pin Types and Boundary Scan Cells
Sequence of Pins in the Boundary Scan
Number of Boundary Scan Cells Usage
1
2
3
Pin
Number
7
8
23
24
25
Pin Name
CL15
PDM3
CODE
SDX
RES
35
Type
I/O
O
I
I
I
Input
Output, enable
Input, output, enable
Number of
Scan Cells
3
2
1
1
1
Functional Description
Rev. 1, 2004-05-28
Default
value
TDI ––>
0 10
0 0
0
0
0
PEB 24902
PEF 24902