PEB24902HV2.1XT Infineon Technologies, PEB24902HV2.1XT Datasheet - Page 15

• Manufacturer Part Number: PEB24902HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEB24902HV2.1XT

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Compliant

Table 3
Pin No. Symbol
19
51
62
JTAG Boundary Scan
57
58
55
56
59
29
28
33
36
20
21
Data Sheet
Note: case of JTAG interface disabled (TDISS = 0), pin TCK should be pulled down
Line Port Pins
on board (e.g. pull-down of 47 k ).
V
V
V
TCK
TMS
TDI
TDO
TDISS
AIN0
BIN0
AOUT0
BOUT0
AIN1
BIN1
REF1
REF2
REF3
Pin Definitions and Functions (cont’d)
Input (I)
Output (O)
N.C.
N.C.
N.C.
I
I (PU)
I (PU)
O
I (PU)
I
I
O
O
I
I
Description
Reference Voltage
No function, a capacitor, 100 nF, may be connected
to GND to maintain compatibility with previous
versions
Reference Voltage
No function, a capacitor, 100 nF, may be connected
to GND to maintain compatibility with previous
versions
Reference Voltage
No function, a capacitor, 100 nF, may be connected
to GND to maintain compatibility with previous
versions
Test Clock
Test Mode Select
Test Data Input
Test Data Output
JTAG Boundary Scan Disable
Active low, internal pullup (I
Differential U interface input
Line port 0
Differential U interface input
Line port 0
Differential U interface output
Line port 0
Differential U interface output
Line port 0
Differential U interface input
Line port 1
Differential U interface input
Line port 1
15
TDISS
= -100 A (typ.))
External Signals
Rev. 1, 2004-05-28
PEB 24902
PEF 24902