DS26521L+ Maxim Integrated Products, DS26521L+ Datasheet - Page 25

• Manufacturer Part Number: DS26521L+
• Description: IC TXRX T1/E1/J1 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26521L+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 220 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS26521 Single T1/E1/J1 Transceiver
8.
FUNCTIONAL DESCRIPTION
8.1
Microprocessor Interface
8.1.1 Parallel Port Mode
Parallel port control of the DS26521 is accomplished through the 26 hardware pins of the microprocessor port. The
8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the bus type select (BTS)
pin. When the BTS pin is a logic 0, bus timing is in Intel mode, as shown in
Figure 12-1
and
Figure
12-2. When the
BTS pin is a logic 1, bus timing is in Motorola mode, as shown in
Figure 12-3
and
Figure
12-4. The address space
is mapped through the use of 10 address lines, A12 and A[8:0]. Multiplexed mode is not supported on the
processor interface.
8.1.2 SPI Serial Port Mode
The external processor bus can be configured to operate in SPI serial bus mode. See Section
8.1.3
for detailed
timing diagrams.
When SPI_SEL = 1, SPI bus mode is implemented using four signals: clock (SPI_CLK), master-out/slave-in data
(SPI_MOSI), master-in/slave-out data (SPI_MISO), and chip select (CSB). Clock polarity and phase can be set by
the D[7]/SPI_CPOL and D[6]/SPI_CPHA pins.
The order of the address and data bits in the serial stream is selectable using the D[5]/SPI_SWAP pin. The R/W bit
is always first and B bit is always last in the initial control word and are not affected by the D[5]/SPI_SWAP pin
setting.
The chip-select bar (CSB) pin must be brought to a logic-low level to gain read and write access to the
microprocessor port. With Intel timing selected, the read-data bar (RDB) and write-read bar (WRB) pins are used to
indicate read and write operations and latch data through the interface. With Motorola timing selected, the read-
write bar (RWB) pin is used to indicate read and write operations while the data-strobe bar (DSB) pin is used to
latch data through the interface.
The interrupt output pin (INTB) is an open-drain output that asserts a logic-low level upon a number of software
maskable interrupt conditions. This pin is normally connected to the microprocessor interrupt input.
8.1.3 SPI Functional Timing Diagrams
Note: The transmit and receive order of the address and data bits are selected by the D[5]/SPI_SWAP pin. The
R/W (read/write) MSB bit position and B (burst) LSB bit position are not affected by the D[5]/SPI_SWAP pin setting.
8.1.3.1 SPI Transmission Format and CPHA Polarity
When CPHA = 0, CSB may be deasserted between accesses. An access is defined as one or two control bytes
followed by a data byte. CSB cannot be deasserted between the control bytes, or between the last control byte and
the data byte. When CPHA = 0, CSB may also remain asserted between accesses. If it remains asserted and the
BURST bit is set, no additional control bytes are expected after the first control byte(s) and data are transferred. If
the BURST bit is set, the address will be incremented for each additional byte of data transferred until CSB is
deasserted. If CSB remains asserted and the BURST bit is not set, a control byte(s) is expected following the data
byte, and the address for the next access will be received from that. Anytime CSB is deasserted, the BURST
access is terminated.
When CPHA = 1, CSB may remain asserted for more than one access without being toggled high and then low
again between accesses. If the BURST bit is set, the address should increment and no additional control bytes are
expected. If the BURST bit is not set, each data byte will be followed by the control byte(s) for the next access.
Additionally, CSB may also be deasserted between accesses when CPHA =1. In the case, any BURST access is
terminated, and the next byte received when CSB is reasserted will be a control byte.
The following diagrams describe the functionality of the SPI port for the four combinations of SPI_CPOL and
SPI_CPHA. They indicate the clock edge that samples the data and the level of the clock during no-transfer events
(high or low). Since the SPI port of the DS26521 acts as a slave device, the master device provides the clock. The
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