DS26521L+ Maxim Integrated Products, DS26521L+ Datasheet - Page 20

• Manufacturer Part Number: DS26521L+
• Description: IC TXRX T1/E1/J1 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26521L+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 220 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TSSYNCIO
TCHBLK/
TSYNC
NAME
TSIG
CLK
PIN
61
60
59
58
TYPE
I/O
I/O
O
I
Transmit Synchronization. A pulse at this pin establishes either frame or
multiframe boundaries for the transmit side. This signal can also be programmed to
output either a frame or multiframe pulse. If this pin is set to output pulses at frame
boundaries, it can also be set to output double-wide pulses at signaling frames in
T1 mode. The operation of this signals is synchronous with TCLK.
Transmit System Synchronization In. Only used when the transmit-side elastic
store is enabled. A pulse at this pin establishes either frame or multiframe
boundaries for the transmit side. Note that if the elastic store is enabled, frame or
multiframe boundary will be established for the transmitter. Should be tied low in
applications that do not use the transmit-side elastic store. The operation of this
signal is synchronous with TSYSCLK.
Transmit System Synchronization Out. If configured as an output, an 8kHz
pulse synchronous to the BPCLK will be generated. This pulse in combination with
BPCLK can be used as an IBO master. The BPCLK can be sourced to RSYSCLK,
TSYSCLK, and TSSYNCIO as a source to RSYNC, and TSSYNCIO of DS26521
or RSYNC and TSSYNC of other Dallas Semiconductor parts.
Transmit Signaling. When enabled, this input samples signaling bits for insertion
into outgoing PCM data stream. Sampled on the falling edge of TCLK when the
transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK
when the transmit-side elastic store is enabled.
Transmit Channel Block/Transmit Channel Block Clock. A dual function pin.
TCHBLK is a user-programmable output that can be forced high or low. It is
synchronous with TCLK when the transmit-side elastic store is disabled. It is
synchronous with TSYSCLK when the transmit-side elastic store is enabled. It is
useful for blocking clocks to a serial UART or LAPD controller in applications
where not all channels are used such as Fractional T1, Fractional E1, 384kbps
(H0), 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-
and-insert applications, for external per-channel loopback, and for per-channel
conditioning.
TCHCLK. TCHCLK is a 192kHz (T1) or 256kHz (E1) clock that pulses high during
the LSB of the channel. It can also be programmed to output a gated transmit bit
clock controlled by TCHBLK. It is synchronous with TCLK when the transmit-side
elastic store is disabled. It is synchronous with TSYSCLK when the transmit-side
elastic store is enabled. Useful for parallel-to-serial conversion of channel data.
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FUNCTION
DS26521 Single T1/E1/J1 Transceiver