PIC12F683-E/P Microchip Technology Inc., PIC12F683-E/P Datasheet - Page 9

• Manufacturer Part Number: PIC12F683-E/P
• Description: 8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O, PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-E/P

• A/d Inputs: 4 Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Serial Interface: None
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.0
2.1
The PIC12F683 has a 13-bit program counter capable
of addressing an 8k x 14 program memory space. Only
the first 2k x 14 (0000h-07FFh) for the PIC12F683 is
physically implemented. Accessing a location above
these boundaries will cause a wrap around within the
first 2k x 14 space. The Reset vector is at 0000h and
the interrupt vector is at 0004h (see Figure 2-1).
FIGURE 2-1:
 2004 Microchip Technology Inc.
CALL, RETURN
RETFIE, RETLW
MEMORY ORGANIZATION
Program Memory Organization
On-chip Program
Interrupt Vector
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
PC<12:0>
Memory
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F683
13
000h
0004
0005
07FFh
0800h
1FFFh
Preliminary
2.2
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the General Purpose Regis-
ters (GPR) and the Special Function Registers (SFR).
The Special Function Registers are located in the first
32 locations of each bank. Register locations 20h-7Fh
in Bank 0 and A0h-BFh in Bank 1 are general purpose
registers, implemented as static RAM. Register loca-
tions F0h-FFh in Bank 1 point to addresses 70h-7Fh in
Bank 0. All other RAM is unimplemented and returns ‘0’
when read. RP0 (Status<5>) is the bank select bit.
• RP0 = 0: Bank 0 is selected
• RP0 = 1: Bank 1 is selected
2.2.1
The register file is organized as 128 x 8 in the
PIC12F683. Each register is accessed, either directly
or indirectly, through the File Select Register FSR (see
Section 2.4 “Indirect Addressing, INDF and FSR
Registers”).
Note:
Data Memory Organization
The IRP and RP1 bits (Status<7:6>) are
reserved
maintained as ‘0’s.
GENERAL PURPOSE REGISTER
FILE
and
PIC12F683
should
DS41211B-page 7
always
be