PIC12F683-E/P Microchip Technology Inc., PIC12F683-E/P Datasheet - Page 17

• Manufacturer Part Number: PIC12F683-E/P
• Description: 8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O, PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-E/P

• A/d Inputs: 4 Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Serial Interface: None
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.2.2.5
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-5.
REGISTER 2-5:
 2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIR1 Register
PIR1 – PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch)
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
ADIF: A/D Interrupt Flag bit
1 = A/D conversion complete
0 = A/D conversion has not completed or has not been started
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
Unimplemented: Read as ‘0’
CMIF: Comparator Interrupt Flag bit
1 = Comparator 1 output has changed (must be cleared in software)
0 = Comparator 1 output has not changed
OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
TMR2IF: Timer 2 to PR2 Match Interrupt Flag bit
1 = Timer 2 to PR2 match occurred (must be cleared in software)
0 = Timer 2 to PR2 match has not occurred
TMR1IF: Timer 1 Overflow Interrupt Flag bit
1 = Timer 1 register overflowed (must be cleared in software)
0 = Timer 1 has not overflowed
Legend:
R = Readable bit
- n = Value at POR
R/W-0
EEIF
R/W-0
ADIF
CCP1IF
R/W-0
Preliminary
W = Writable bit
‘1’ = Bit is set
U-0
—
Note:
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CMIF
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
OSFIF
R/W-0
PIC12F683
x = Bit is unknown
TMR2IF
R/W-0
DS41211B-page 15
TMR1IF
R/W-0
bit 0