PIC18F2420-I/SP Microchip Technology Inc., PIC18F2420-I/SP Datasheet - Page 84
PIC18F2420-I/SP
Manufacturer Part Number
PIC18F2420-I/SP
Description
28 Pin, 16 KB Flash, 768 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2420-ISP.pdf
(388 pages)
Specifications of PIC18F2420-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2420-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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- Download datasheet (7Mb)
PIC18F2220/2320/4220/4320
REGISTER 7-1:
DS39599C-page 82
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EECON1 REGISTER
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access program Flash memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EE or Configuration Select bit
1 = Access configuration or calibration registers
0 = Access program Flash or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared
0 = Perform write only
WRERR: EEPROM Error Flag bit
1 = A write operation was prematurely terminated
0 = The write operation completed normally
WREN: Erase/Write Enable bit
1 = Allows erase/write cycles
0 = Inhibits erase/write cycles
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
0 = Write cycle is completed
RD: Read Control bit
1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can
0 = Read completed
Legend:
R = Readable bit
- n = Value at POR
bit 7
EEPGD
Note:
R/W-x
by completion of erase operation)
(MCLR or WDT Reset during self-timed erase or program operation)
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
R/W-x
CFGS
S = Settable only
‘1’ = Bit is set
U-0
—
R/W-0
FREE
U = Unimplemented bit, read as ‘0’ W = Writable bit
‘0’ = Bit is cleared
WRERR
R/W-x
WREN
R/W-0
2003 Microchip Technology Inc.
R/S-0
WR
x = Bit is unknown
R/S-0
RD
bit 0
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