PIC18F2420-I/SP Microchip Technology Inc., PIC18F2420-I/SP Datasheet - Page 130
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PIC18F2420-I/SP
Manufacturer Part Number
PIC18F2420-I/SP
Description
28 Pin, 16 KB Flash, 768 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2420-ISP.pdf
(388 pages)
Specifications of PIC18F2420-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2420-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18F2220/2320/4220/4320
13.2
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
FIGURE 13-1:
TABLE 13-1:
DS39599C-page 128
INTCON
PIR1
PIE1
IPR1
TMR2
T2CON
PR2
OSCCON
Legend:
Note 1:
Name
Timer2 Interrupt
Timer2 Module Register
Timer2 Period Register
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
GIE/GIEH PEIE/GIEL
PSPIE
PSPIP
PSPIF
Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.
F
IDLEN
Bit 7
OSC
—
/4
(1)
(1)
(1)
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
TIMER2 BLOCK DIAGRAM
IRCF2
ADIF
ADIE
ADIP
Bit 6
T2CKPS1:T2CKPS0
1:1, 1:4, 1:16
Prescaler
TMR0IE
IRCF1
RCIF
RCIE
RCIP
Bit 5
2
INT0IE
IRCF0
Bit 4
TXIF
TXIE
TXIP
Comparator
TMR2
PR2
SSPIF
SSPIE
SSPIP
OSTS
RBIE
Bit 3
13.3
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate the shift clock.
EQ
Reset
TMR0IF
CCP1IE
CCP1IP
CCP1IF
TOUTPS3:TOUTPS0
IOFS
Bit 2
Postscaler
1:1 to 1:16
Output of TMR2
Output
TMR2IF
TMR2IE
TMR2IP
INT0IF
TMR2
SCS1
Bit 1
4
(1)
TMR1IE
TMR1IP
TMR1IF
SCS0
Bit 0
RBIF
2003 Microchip Technology Inc.
bit TMR2IF
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
0000 qq00 0000 qq00
Sets Flag
POR, BOR
Value on
Value on
all other
Resets
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