DS2148T+ Maxim Integrated Products, DS2148T+ Datasheet - Page 44

• Manufacturer Part Number: DS2148T+
• Description: IC LIU E1/T1/J1 5V 44-TQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS2148T+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.3 Analog Loopback (ALB)
Setting ALB (CCR6.4) to a one puts the DS2148 in Analog Loopback. Signals at TTIP and TRING will
be internally connected to RTIP and RRING. The incoming signals at RTIP and RRING will be ignored.
The signals at TTIP and TRING will be transmitted as normal. (See
6.2.4 Dual Loopback (DLB)
Setting both CCR6.7 and CCR6.6 to a one, LLB and RLB respectively, puts the DS2148 into dual
loopback operation. The TCLK and TPOS/TNEG signals will be looped back through the jitter attenuator
(if enabled) and output at RCLK and RPOS/RNEG. Clock and data recovered from RTIP and RRING
will be looped back to the transmit-side and output at TTIP and TRING. This mode of operation is not
available when implementing hardware operation. (See
6.3 PRBS Generation and Detection
Setting TPRBSE (CCR3.4) = 1 enables the DS2148 to transmit a 2
Random Bit Sequence (PRBS) depending on the ETS bit setting in CCR1.7. The receive-side of the
DS2148 will always search for these PRBS patterns independent of CCR3.4. The PRBS Bit Error Output
(PBEO) will remain high until the receiver has synchronized to one of the two patterns (64 bits received
without an error) at which time PBEO will go low and the PRBSD bit in the status register (SR) will be
set. Once synchronized, any bit errors received will cause a positive going pulse at PBEO, synchronous
with RCLK. This output can be used with external circuitry to keep track of bit error rates during the
PRBS testing. Setting CCR6.0 (ECRS) = 1 will allow the PRBS errors to be accumulated in the 16-bit
counter in registers ECR1 and ECR2. The PRBS synchronizer will remain in sync until it experiences 6
bit errors or more within a 64-bit span. Both PRBS patterns comply with the ITU-T O.151 specifications.
6.4 Error Counter
Error Count Register 1 (ECR1) is the most significant word and ECR2 is the least significant word of a
user-selectable 16-bit counter that records incoming errors including Bipolar Violations (BPV), Code
Violations (CV), Excessive Zero violations (EXZ) and/or PRBS Errors. See
Figure 1-2
Table 6-3. Definition of Received Errors
ERROR
PRBS
BPV
EXZ
EXZ
CV
for details.
E1 OR T1
E1/T1
E1/T1
E1
E1
T1
Two consecutive marks with the same polarity. Will ignore BPVs due to
HDB3 and B8ZS zero suppression when CCR2.3 = 0. Typically used with
AMI coding (CCR2.3 = 1). ITU-T O.161.
When HDB3 is enabled (CCR2.3 = 0) and the receiver detects two
consecutive BPVs with the same polarity. ITU-T O.161.
When four or more consecutive zeros are detected.
When receiving AMI coded signals (CCR2.3 = 1), detection of 16 or more
zeros or a BPV. ANSI T1.403 1999.
When receiving B8ZS coded signals (CCR2.3 = 0), detection of 8 or more
zeros or a BPV. ANSI T1.403 1999.
A bit error in a received PRBS pattern. See Section
ITU-T O.151.
DEFINITION OF RECEIVED ERRORS
44 of 73
Figure
1-1.)
Figure
15
-1 (E1) or a 2
1-1.)
Table 6-3
6.3
for details.
and
20
-1 (T1) Pseudo
Table 6-4
and