PIC18F452-I/L Microchip Technology Inc., PIC18F452-I/L Datasheet - Page 135

• Manufacturer Part Number: PIC18F452-I/L
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/L

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.3.8
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
Normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode and data to be
shifted into the SPI transmit/receive shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from SLEEP.
15.3.9
A RESET disables the MSSP module and terminates
the current transfer.
TABLE 15-2:
© 2006 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISC
SSPBUF
SSPCON
TRISA
SSPSTAT
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices; always maintain these bits clear.
Name
SLEEP OPERATION
EFFECTS OF A RESET
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
GIE/GIEH
PSPIF
PSPIE
PSPIP
WCOL
Bit 7
SMP
—
REGISTERS ASSOCIATED WITH SPI OPERATION
(1)
(1)
(1)
PORTA Data Direction Register
SSPOV
PEIE/
ADIE
ADIP
GIEL
ADIF
Bit 6
CKE
TMR0IE
SSPEN
RCIF
RCIE
RCIP
Bit 5
D/A
INT0IE
TXIE
TXIP
Bit 4
TXIF
CKP
P
SSPM3
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
S
15.3.10
Table 15-1 shows the compatibility between the
standard SPI modes and the states the CKP and CKE
control bits.
TABLE 15-1:
There is also a SMP bit which controls when the data is
sampled.
TMR0IF
CCP1IE
CCP1IP
CCP1IF
SSPM2
Standard SPI Mode
Bit 2
R/W
Terminology
0, 0
0, 1
1, 0
1, 1
TMR2IF
TMR2IE
TMR2IP
SSPM1
INT0IF
BUS MODE COMPATIBILITY
Bit 1
UA
SPI BUS MODES
TMR1IF
TMR1IE
TMR1IP
SSPM0
RBIF
Bit 0
BF
PIC18FXX2
CKP
Control Bits State
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
-111 1111 -111 1111
0000 0000 0000 0000
POR, BOR
0
0
1
1
Value on
DS39564C-page 133
All Other
CKE
Value on
RESETS
1
0
1
0