PIC18F452-I/L Microchip Technology Inc., PIC18F452-I/L Datasheet - Page 119

• Manufacturer Part Number: PIC18F452-I/L
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/L

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

14.0
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit Capture
register, as a 16-bit Compare register or as a PWM
Master/Slave Duty Cycle register. Table 14-1 shows
the timer resources of the CCP Module modes.
REGISTER 14-1:
© 2006 Microchip Technology Inc.
CAPTURE/COMPARE/PWM
(CCP) MODULES
bit 7-6
bit 5-4
bit 3-0
CCP1CON REGISTER/CCP2CON REGISTER
bit 7
Unimplemented: Read as '0'
DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode,
1001 = Compare mode,
1010 = Compare mode,
1011 = Compare mode,
11xx = PWM mode
Legend:
R = Readable bit
- n = Value at POR
U-0
—
Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set)
Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set)
Generate software interrupt on compare match (CCPIF bit is set, CCP pin is unaffected)
Trigger special event (CCPIF bit is set)
U-0
—
DCxB1
R/W-0
W = Writable bit
’1’ = Bit is set
DCxB0
R/W-0
The operation of CCP1 is identical to that of CCP2, with
the exception of the special event trigger. Therefore,
operation of a CCP module in the following sections is
described with respect to CCP1.
Table 14-2 shows the interaction of the CCP modules.
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
CCPxM3
R/W-0
CCPxM2 CCPxM1 CCPxM0
R/W-0
PIC18FXX2
x = Bit is unknown
R/W-0
DS39564C-page 117
R/W-0
bit 0