AN82527F8 Intel, AN82527F8 Datasheet
AN82527F8
Specifications of AN82527F8
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AN82527F8 Summary of contents
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... Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata ...
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Figure 1 82527 Block Diagram Figure 2 44-Pin PLCC Package 272250 – 1 272250 –2 ...
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Figure 3 44-Pin QFP Package 82527 272250 –15 3 ...
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PIN DESCRIPTION The 82527 pins are described in this section Table 1 presents the legend for interpreting the pin types Symbol PIN DESCRIPTIONS Pin Name Pin Type V Ground GROUND connection must be connected externally ...
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... These pins select one of the four parallel interfaces These pins are weakly held low during reset Mode1 I Mode1 ALE AS I-I ALE used for Intel modes AS used for non-Intel modes except Mode 3 this pin must be tied high used for non-Intel modes except Mode 3 Asynchronous this pin must be tied high WR WRL ...
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ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Storage Temperature Voltage from Any Pin Laboratory testing shows the 82527 will withstand injected current into both RX0 ...
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D C Characteristics Symbol Parameter (1) I Supply Current CC (1) I Sleep Current SLEEP with V 2 Output Enabled No Load CC with V 2 Output Disabled CC (1) I Powerdown Current PD NOTES Typical ...
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... A C Characteristics for 8 16-Bit Multiplexed Intel Modes (Modes 0 1) Conditions Symbol Parameter 1 t Oscillator Frequency XTAL 1 t System Clock Frequency SCLK 1 t Memory Clock Frequency MCLK t Address Valid to ALE Low AVLL t Address Hold after ALE Low LLAX t ALE High Time ...
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... Definition of ‘‘write cycle with a previous write’’ The time between the rising edge of WR cycle) and the rising edge of WR WRH 3 Definition the value loaded in the CLKOUT register representing the CLKOUT divisor Characteristics for 8 16-Bit Multiplexed Intel Modes (Modes 125 C C 100 pF (Continued ...
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... A C Characteristics for 8 16-Bit Multiplexed Intel Modes (Modes 0 1) Ready Output Timing for a Write Cycle if No Previous Write is Pending Ready Output Timing for a Write Cycle if a Previous Write Cycle is Active Ready Output Timing for a Read Cycle 10 272250 –4 272250 –5 ...
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... A C Characteristics for 8-Bit Multiplexed Non-Intel Mode (Mode 2) Conditions Symbol Parameter 1 t Oscillator Frequency XTAL 1 t System Clock Frequency SCLK 1 t Memory Clock Frequency MCLK t Address Valid to AS Low AVSL t Address Hold after AS Low SLAX t Data Float after E Low ELDZ ...
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... A C Characteristics for 8-Bit Multiplexed Non-Intel Mode (Mode 2) 12 272250 –7 ...
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A C Characteristics for 8-Bit Non-Multiplexed Asynchronous (Mode 3) Conditions Symbol Parameter 1 t Oscillator Frequency XTAL 1 t System Clock Frequency SCLK 1 t Memory Clock Frequency MCLK t Address ...
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A C Characteristics for 8-Bit Non-Multiplexed Asynchronous Mode (Mode 3) Timing of the Asynchronous Mode A C Characteristics for 8-Bit Non-Multiplexed Asynchronous Mode (Mode 3) Timing of the Asynchronous Mode 14 (Read Cycle) (Write Cycle) 272250 –10 272250 –11 ...
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A C Characteristics for 8-Bit Non-Multiplexed Synchronous Mode (Mode 3) Conditions Symbol Parameter 1 t Oscillator Frequency XTAL 1 t System Clock Frequency SCLK 1 t Memory Clock Frequency MCLK t ...
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A C Characteristics for 8-Bit Non-Multiplexed Synchronous Mode (Mode 3) Timing of the Synchronous Mode A C Characteristics for 8-Bit Non-Multiplexed Synchronous Mode (Mode 3) Timing of the Synchronous Mode 16 (Read Cycle) (Write Cycle) 272250 –8 272250 –9 ...
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A C Characteristics for Serial Interface Mode Conditions Symbol Parameter SCLK SPI Clock t 1 SCLK CYC t Minimum Clock High Time SKHI t Minimum Clock Low Time SKLO t ENABLE ...
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A C Characteristics for Serial Interface Mode A C TESTING INPUT Input Output Waveforms NOTE AC Inputs during testing are driven Logic ‘‘1’’ and 0 1V for a Logic ‘‘0’’ Timing measure- ments are made at ...
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Removed XTAL1 and XTAL2 from the excep- tions for V spec XTAL1 V is now specified min 0 5V max 0 8V XTAL2 is an output Removed XTAL1 and XTAL2 from the ...
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... WRL ) ( from WR and WR in 8-bit Intel mode and WRL 16-bit Intel mode replaces the description WR used for Intel modes 19 Page 5 ABSOLUTE MAXIMUM RATINGS addi- tion Laboratory testing shows the 82527 will withstand for injected current into ...
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... Delay Dominant to Recessive b Delay Recessive to Dominant c Input Delay with Comparator Bypassed d Rise Time e Fall Time 13 The following A C Characteristics for 8-Bit 16-Bit Multiplexed Intel Modes (Modes 0 1) have been changed has been increased to 8 MHz from MCLK 5 MHz b t ...
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... The timing diagrams for 8-Bit 16-Bit Multiplexed Intel Modes (Modes 0 1) have been changed to show ALE rising before CS falls 15 The following A C Characteristics for 8-Bit Mul- tiplexed Non-Intel Modes (Modes 2) have been changed has been increased to 8 MHz from MCLK ...