71M6521FE-IM Maxim Integrated Products, 71M6521FE-IM Datasheet - Page 48

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71M6521FE-IM

Manufacturer Part Number
71M6521FE-IM
Description
Current & Power Monitors & Regulators Residential Energy Meter IC
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of 71M6521FE-IM

Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
783-71M6521FE-IM/F, 783-71M6521FE-IMR, 783-71M6521FE-IMR/F 783-71M6521FEIM-DB,

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
71M6521FE-IM/F
Manufacturer:
MAXIM
Quantity:
2 000
Part Number:
71M6521FE-IMR/F
Manufacturer:
NOMA
Quantity:
700
Figure 16 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two serial output
streams. In this example, MUX_DIV=4 and FIR_LEN=1 (384). The duration of each MUX frame is 1 + MUX_DIV * 2 if
FIR_LEN=288, and 1 + MUX_DIV * 3 if FIR_LEN=384. An ADC conversion will always consume an integer number of CK32
clocks. Followed by the conversions is a single CK32 cycle where the bandgap voltage is allowed to recover from the change
in CROSS.
Each CE program pass begins when ADC0 (channel IA) conversion begins. Depending on the length of the CE program, it
may continue running until the end of the ADC3 (VB) conversion. CE opcodes are constructed to ensure that all CE code
passes consume exactly the same number of cycles. The result of each ADC conversion is inserted into the CE DRAM when
the conversion is complete. The CE code is written to tolerate sudden changes in ADC data. The exact CK count when each
ADC value is loaded into DRAM is shown in Figure 16.
Figure 16 also shows that the serial RTM data stream begins transmitting at the beginning of state ‘S.’ RTM, consisting of 140
CK cycles, will always finish before the next code pass starts.
Page: 48 of 101
ADC TIMING
RTM TIMING
CE TIMING
ADC EXECUTION
CE_EXECUTION
NOTES:
XFER_BUSY
MUX STATE
MUX_SYNC
CE_BUSY
CK32
RTM
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.
Figure 16: Timing Relationship between ADC MUX, Compute Engine, and Serial Transfers.
S
0
150
0
CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5)
© 2005-2008 TERIDIAN Semiconductor Corporation
ADC0
450
System Timing Summary
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
MUX_DIV
1
Conversions, MUX_DIV=1 (4 conversions) is shown
ADC MUX Frame
ADC1
900
71M6521DE/71M6521FE
2
Energy Meter IC
ADC2
1350
MAX CK COUNT
DATASHEET
3
JANUARY 2008
ADC3
1800
Settle
140
S
v1.0

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