STE10/100A STMicroelectronics, STE10/100A Datasheet - Page 66

• Manufacturer Part Number: STE10/100A
• Description: IC CTRLR PCI ETHERNET 128-PQFP
• Manufacturer: STMicroelectronics

Specifications of STE10/100A

• Controller Type: Ethernet Controller, 10Base-T
• Interface: PCI
• Voltage - Supply: 3.14 V ~ 3.46 V
• Current - Supply: 130mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-3663

Registers and descriptors description
4.4
4.4.1
Note:
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Descriptors and buffer management
The STE10/100A provides receive and transmit descriptors for packet buffering and
management.
Receive descriptor
Table 11.
Descriptors and receive buffers addresses must be long-word aligned
Table 12.
RDES0
RDES0
RDES1
RDSE2
RDSE3
30-16
13-12
Bit#
31
15
14
11
10
Own
Receive descriptor table
Receive descriptor description
Name
31
OWN
MF
ES
DE
DT
RF
FL
---
Own bit
1: indicates that newly received data can be put into this descriptor
0: Host has not yet processed the received data currently in this descriptor.
Frame length, including CRC. This field is valid only in a frame’s last
descriptor.
Error summary. Logical OR of the following bits:
This field is valid only in a frame’s last descriptor.
Descriptor error. This bit is valid only in a frame’s last descriptor.
1: the current valid descriptor is unable to contain the packet being currently
received. The packet is truncated.
Data type
00: normal
01: MAC loop-back
10: Transceiver loop-back
11: remote loop-back
These bits are valid only in a frame’s last descriptor.
Runt frame (packet length < 64 bytes). This bit is valid only in a frame’s last
descriptor.
Multicast frame. This bit is valid only in a frame’s last descriptor.
0: overflow
1: CRC error
6: late collision
7: frame too long
11: runt packet
14: descriptor error
Control
Buffer1 address (DW boundary)
Buffer2 address (DW boundary)
Buffer2 byte-count
Description
Status
Buffer1 byte-count
STE10/100A
0